R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 494

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(3)
The timing for transfer from buffer registers to timer general registers can be selected in PWM
mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation
transfer mode registers (TBTM_0, TBTM_3, and TBTM_4). Either compare match (initial
setting) or TCNT clearing can be selected for the transfer timing. TCNT clearing as transfer
timing is one of the following cases.
• When TCNT overflows (H'FFFF to H'0000)
• When H'0000 is written to TCNT during counting
• When TCNT is cleared to H'0000 under the condition specified in the CCLR2 to CCLR0 bits
Note: TBTM must be modified only while TCNT stops.
Figure 12.19 shows an operation example in which PWM mode 1 is designated for channel 0 and
buffer operation is designated for TGRA_0 and TGRC_0. The settings used in this example are
TCNT_0 clearing by compare match B, 1 output at compare match A, and 0 output at compare
match B. The TTSA bit in TBTM_0 is set to 1.
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in TCR
Figure 12.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for
Selecting Timing for Transfer from Buffer Registers to Timer General Registers in
Buffer Operation:
TGRC_0
TGRA_0
TIOCA
TGRB_0
TGRA_0
H'0000
TCNT_0 value
H'0200
H'0200
H'0200
TGRC_0 to TGRA_0 Transfer Timing
H'0450
H'0450
Transfer
H'0450
H'0520
H'0520
R01UH0026EJ0300 Rev. 3.00
H'0520
SH7201 Group
Time
Sep 24, 2010