R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 520

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
(b)
In complementary PWM mode, nine registers are used, comprising compare registers, buffer
registers, and temporary registers. Figure 12.40 shows an example of complementary PWM mode
operation.
The registers which are constantly compared with the counters to perform PWM output are
TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits
OLSN and OLSP in the timer output control register (TOCR) is output.
The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4.
Between a buffer register and compare register there is a temporary register. The temporary
registers cannot be accessed by the CPU.
Data in a compare register is changed by writing the new data to the corresponding buffer register.
The buffer registers can be read or written at any time.
The data written to a buffer register is constantly transferred to the temporary register in the Ta
interval. Data is not transferred to the temporary register in the Tb interval. Data written to a
buffer register in this interval is transferred to the temporary register at the end of the Tb interval.
The value transferred to a temporary register is transferred to the compare register when TCNTS
for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting
down. The timing for transfer from the temporary register to the compare register can be selected
with bits MD3 to MD0 in the timer mode register (TMDR). Figure 12.40 shows an example in
which the mode is selected in which the change is made in the trough.
In the Tb interval (Tb1 in figure 12.40) in which data transfer to the temporary register is not
performed, the temporary register has the same function as the compare register, and is compared
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Counter value
TGRA_3
H'0000
TCDR
TDDR
Register Operation
Figure 12.39 Complementary PWM Mode Counter Operation
TCNT_4
TCNTS
TCNT_3
R01UH0026EJ0300 Rev. 3.00
TCNT_3
TCNT_4
TCNTS
SH7201 Group
Sep 24, 2010
Time