R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 719

• Manufacturer Part Number: R0K572011S000BE
• Description: KIT STARTER FOR SH7201
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572011S000BE

• Contents: CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
• For Use With/related Products: SH7201
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SH7201 Group
Note:
R01UH0026EJ0300 Rev. 3.00
Sep 24, 2010
Bit
0
* Only 0 can be written to clear the flag after 1 is read.
Bit Name
DR
Initial
Value
0
R/W
R/(W)* Receive Data Ready
Description
Indicates that the quantity of data in the receive FIFO
data register (SCFRDR) is less than the specified
receive trigger number, and that the next data has not
yet been received after the elapse of 15 ETU from the
last stop bit in asynchronous mode. In clocked
synchronous mode, this bit is not set to 1.
0: Receiving is in progress, or no receive data
[Clearing conditions]
•
•
•
1: Next receive data has not been received
[Setting condition]
•
Note:1. This is equivalent to 1.5 frames with the 8-bit,
remains in SCFRDR after receiving ended normally
DR is cleared to 0 when the chip undergoes a
power-on reset
DR is cleared to 0 when all receive data are read
after 1 is read from DR and then 0 is written
DR is cleared to 0 when all receive data in
SCFRDR are read after the DMAC is activated by
the receive FIFO data full interrupt (RXI)
DR is set to 1 when SCFRDR contains less data
than the specified receive trigger number, and the
next data has not yet been received after the
elapse of 15 ETU from the last stop bit. *
Section 16 Serial Communication Interface with FIFO (SCIF)
1-stop-bit format. (ETU: Elementary time unit)
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