R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 870
R0K572011S000BE
Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets
1.R0K572011S000BE.pdf
(1222 pages)
2.R0K572011S000BE.pdf
(7 pages)
3.R0K572011S000BE.pdf
(5 pages)
Specifications of R0K572011S000BE
Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 870 of 1222
- Download datasheet (8Mb)
Section 19 Controller Area Network (RCAN-ET)
Bit 6 - Bus Off Interrupt Flag (IRR6): This bit is set when RCAN-ET enters the Bus-off state or
when RCAN-ET leaves Bus-off and returns to Error-Active. The cause therefore is the existing
condition TEC ≥ 256 at the node or the end of the Bus-off recovery sequence (128 × 11
consecutive recessive bits) or the transition from Bus Off to Halt (automatic or manual). This bit
remains set even if the RCAN-ET node leaves the bus-off condition, and needs to be explicitly
cleared by S/W. The S/W is expected to read the GSR0 to judge whether RCAN-ET is in the bus-
off or error active status. It is cleared by writing a '1' to this bit position even if the node is still
bus-off. Writing a '0' has no effect.
Bit 5 - Error Passive Interrupt Flag (IRR5): Interrupt flag indicating the error passive state
caused by the transmit or receive error counter or by Error Passive forced by test mode. This bit is
reset by writing a '1' to this bit position, writing a '0' has no effect. If this bit is cleared the node
may still be error passive. Please note that the SW needs to check GSR0 and GSR5 to judge
whether RCAN-ET is in Error Passive or Bus Off status.
Bit 4 - Receive Error Counter Warning Interrupt Flag (IRR4): This bit becomes set if the
receive error counter (REC) reaches a value greater than 95 when RCAN-ET is not in the Bus Off
status. The interrupt is reset by writing a '1' to this bit position, writing '0' has no effect.
Page 842 of 1190
Bit 6: IRR6
0
1
Bit 5: IRR5
0
1
Bit 4: IRR4
0
1
Description
[Clearing condition] Writing 1 (Initial value)
Enter Bus off state caused by transmit error or Error Active state returning
from Bus-off
[Setting condition] When TEC becomes ≥ 256 or End of Bus-off after 128×
11 consecutive recessive bits or transition from Bus Off to Halt
Description
[Clearing condition] Writing 1 (Initial value)
Error passive state caused by transmit/receive error
[Setting condition] When TEC ≥ 128 or REC ≥ 128 or Error Passive test
mode is used
Description
[Clearing condition] Writing 1 (Initial value)
Error warning state caused by receive error
[Setting condition] When REC ≥ 96 and RCAN-ET is not in Bus Off
R01UH0026EJ0300 Rev. 3.00
SH7201 Group
Sep 24, 2010
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