E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 1009

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SSR2—Serial Status Register 2
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
Transmit Data Register Empty
0
1
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
:
:
:
R/(W)*
TDRE
7
1
Receive Data Register Full
0
1
R/(W)*
RDRF
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When the DMAC or DTC is activated by an RXI interrupt and read data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred
from RSR to RDR
6
0
Overrun Error
0
1
R/(W)*
ORER
[Clearing condition]
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception completed while RDRF = 1
5
0
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state.
Error Signal Status
0
1
R/(W)*
ERS
[Clearing conditions]
• On reset, or in standby mode or module stop mode
• When 0 is written to ERS after reading ERS =1
[Setting condition]
When the error signal is sampled at the low level
4
0
Parity Error
0
1
R/(W)*
[Clearing condition]
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit
does not match the parity setting (even or odd) specified by the O/E bit in SMR
PER
3
0
Note: etu: Elementary Time Unit (the time taken to transmit one bit)
Transmit End
0
1
TEND
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DMAC or DTC is activated by a TXI interrupt and write data to TDR
[Setting conditions]
• On reset, or in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 and ERS = 0, 2.5 etu after a 1-byte serial
R
2
1
transmit character is sent (normal transmission)
Multiprocessor Bit
0
1
MPB
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
R
1
0
H'FF8C
Multiprocessor Bit Transfer
Rev. 5.00 Sep 14, 2006 page 979 of 1060
0
1
MPBT
R/W
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
0
0
Appendix B Internal I/O Register
Smart Card Interface 2
REJ09B0331-0500