E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 1040
E62655RUSB
Manufacturer Part Number
E62655RUSB
Description
EMULATOR BASE H8S/2655R W/USB
Manufacturer
Renesas Electronics America
Type
Microcontrollerr
Datasheet
1.E62655RUSB.pdf
(1093 pages)
Specifications of E62655RUSB
Contents
E6000 Emulator Unit and 4 Logic Probes
For Use With/related Products
H8S/2655R
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 1040 of 1093
- Download datasheet (6Mb)
Appendix B Internal I/O Register
TSR2—Timer Status Register 2
Rev. 5.00 Sep 14, 2006 page 1010 of 1060
REJ09B0331-0500
Bit
Initial value
Read/Write
Note:
*
Can only be written with 0 for flag clearing.
:
:
:
Count Direction Flag
TCFD
0
1
R
7
1
TCNT counts down
TCNT counts up
—
—
6
1
Underflow Flag
R/(W)*
TCFU
0
1
5
0
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Overflow Flag
R/(W)*
TCFV
0
1
4
0
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
—
—
3
0
—
—
2
0
TGR Input Capture/Output Compare Flag B
R/(W)*
H'FFF5
TGFB
0
1
1
0
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL
• When 0 is written to TGFB after reading
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
• When TCNT value is transferred to TGRB by input
TGR Input Capture/Output Compare Flag A
bit of MRB in DTC is 0
TGFB = 1
output compare register
capture signal while TGRB is functioning as input
capture register
0
1
R/(W)*
TGFA
0
0
[Clearing conditions]
• When DTC is activated by TGIA interrupt
• When DMAC is activated by TGIA interrupt
• When 0 is written to TGFA after reading
[Setting conditions]
• When TCNT = TGRA while TGRA is
• When TCNT value is transferred to TGRA by
while DISEL bit of MRB in DTC is 0
while DTA bit of DMABCR in DMAC is 1
TGFA = 1
functioning as output compare register
input capture signal while TGRA is functioning
as input capture register
TPU2
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