E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 150

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 5 Interrupt Controller
[1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
[2] When interrupt requests are sent to the interrupt controller, it performs interrupt acceptance
[3] The interrupt request with the highest priority according to the priority levels set in IPR is
[4] If the I bit is cleared to 0, the priority level of the selected interrupt request is compared with
[5] When an interrupt request is accepted, interrupt exception handling starts after execution of the
[6] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
[7] Next, the I and UI bits in CCR are set to 1. This masks all interrupts except NMI. Also, bits I2
[8] The T bit in EXR is cleared to 0.
[9] A vector address is generated for the accepted interrupt, and execution of the interrupt
[10]If interrupts are enabled again in the interrupt handling routine, the control level of the
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interrupt request is sent to the interrupt controller.
control.
If the I bit is cleared to 0, all interrupts are accepted.
If the I bit is set to 1 and the UI bit is cleared to 0, control level 1 interrupts are accepted.
If both the I bit and the UI bit are set to 1, only an NMI interrupt is accepted.
selected.
the interrupt mask level set in bits I2 to I0. An interrupt request with a priority no higher than
the mask level set at that time is held pending, and only an interrupt request with a priority
higher than the interrupt mask level is accepted.
current instruction has been completed.
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
to I0 are rewritten with the priority of the accepted interrupt. If the accepted interrupt is NMI,
the interrupt mask level is set to H'7.
handling routine starts at the address indicated by the contents of that vector address.
interrupt to be enabled is set to 1, and the UI bit in CCR is cleared to 0. At control level 1, the
interrupt with the highest priority according to the priority level is selected. Bits I2 to I0 are
disabled, and the interrupt mask level is regarded as 0.
When the I bit is cleared to 0, the control level is ignored and an interrupt with a priority level
higher than the mask level set in bits I2 to I0 is accepted.