E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 18

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.2
6.3
6.4
6.5
6.6
Rev. 5.00 Sep 14, 2006 page xvi of xxviii
Register Descriptions ........................................................................................................ 135
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
6.2.8
6.2.9
Overview of Bus Control .................................................................................................. 152
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
Basic Bus Interface ........................................................................................................... 158
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
DRAM Interface ............................................................................................................... 171
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
6.5.10 Burst Operation.................................................................................................... 182
6.5.11 Caution Concerning 2-CAS System..................................................................... 185
6.5.12 Refresh Control.................................................................................................... 186
Pseudo-SRAM Interface ................................................................................................... 190
6.6.1
6.6.2
6.6.3
6.6.4
Bus Width Control Register (ABWCR)............................................................... 135
Access State Control Register (ASTCR) ............................................................. 136
Wait Control Registers H and L (WCRH, WCRL).............................................. 137
Bus Control Register H (BCRH).......................................................................... 140
Bus Control Register L (BCRL) .......................................................................... 143
Memory Control Register (MCR)........................................................................ 145
DRAM Control Register (DRAMCR) ................................................................. 148
Refresh Timer/Counter (RTCNT)........................................................................ 151
Refresh Time Constant Register (RTCOR) ......................................................... 151
Area Partitioning.................................................................................................. 152
Bus Specifications................................................................................................ 153
Memory Interfaces ............................................................................................... 154
Advanced Mode................................................................................................... 155
Areas in Normal Mode......................................................................................... 156
Chip Select Signals .............................................................................................. 157
Overview.............................................................................................................. 158
Data Size and Data Alignment............................................................................. 158
Valid Strobes....................................................................................................... 160
Basic Timing........................................................................................................ 161
Wait Control ........................................................................................................ 169
Overview.............................................................................................................. 171
Setting DRAM Space........................................................................................... 171
Address Multiplexing........................................................................................... 172
Data Bus............................................................................................................... 172
Pins Used for DRAM Interface............................................................................ 173
Basic Timing........................................................................................................ 174
Precharge State Control ....................................................................................... 175
Wait Control ........................................................................................................ 176
Byte Access Control ............................................................................................ 178
Overview.............................................................................................................. 190
Setting PSRAM Space ......................................................................................... 190
Data Bus............................................................................................................... 190
Pins Used for PSRAM Interface .......................................................................... 191