E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 19

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.7
6.8
6.9
6.10 Write Data Buffer Function .............................................................................................. 209
6.11 Bus Release....................................................................................................................... 210
6.12 Bus Arbitration.................................................................................................................. 213
6.13 Resets and the Bus Controller ........................................................................................... 215
Section 7 DMA Controller
7.1
7.2
6.6.5
6.6.6
6.6.7
6.6.8
6.6.9
6.6.10 Power-On Sequence............................................................................................. 200
DMAC Single Address Mode and DRAM/PSRAM Interface.......................................... 201
6.7.1
6.7.2
Burst ROM Interface......................................................................................................... 203
6.8.1
6.8.2
6.8.3
Idle Cycle .......................................................................................................................... 206
6.9.1
6.9.2
6.11.1 Overview.............................................................................................................. 210
6.11.2 Operation ............................................................................................................. 210
6.11.3 Pin States in External Bus Released State............................................................ 211
6.11.4 Transition Timing ................................................................................................ 212
6.12.1 Overview.............................................................................................................. 213
6.12.2 Operation ............................................................................................................. 213
6.12.3 Bus Transfer Timing ............................................................................................ 214
6.12.4 External Bus Release Usage Note........................................................................ 215
Overview........................................................................................................................... 217
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Register Descriptions (1) (Short Address Mode) .............................................................. 223
7.2.1
7.2.2
7.2.3
7.2.4
Basic Timing........................................................................................................ 192
Precharge State Control ....................................................................................... 193
Wait Control ........................................................................................................ 194
Burst Operation.................................................................................................... 196
Refresh Control.................................................................................................... 199
When DDS = 1..................................................................................................... 201
When DDS = 0..................................................................................................... 202
Overview.............................................................................................................. 203
Basic Timing........................................................................................................ 203
Wait Control ........................................................................................................ 205
Operation ............................................................................................................. 206
Pin States in Idle Cycle ........................................................................................ 208
Features................................................................................................................ 217
Block Diagram ..................................................................................................... 218
Overview of Functions......................................................................................... 219
Pin Configuration................................................................................................. 221
Register Configuration......................................................................................... 222
Memory Address Registers (MAR) ..................................................................... 224
I/O Address Register (IOAR) .............................................................................. 225
Execute Transfer Count Register (ETCR) ........................................................... 226
DMA Control Register (DMACR)....................................................................... 227
................................................................................................ 217
Rev. 5.00 Sep 14, 2006 page xvii of xxviii