E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 320

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Section 7 DMA Controller
DREQ
DREQ
DREQ
DREQ Level Activation Timing (Normal Mode)
Set the DTA bit for the channel for which the DREQ pin is selected to 1.
Figure 7.25 shows an example of DREQ level activated normal mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Rev. 5.00 Sep 14, 2006 page 290 of 1060
REJ09B0331-0500
Address bus
DMA control
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Channel
DREQ
Figure 7.25 Example of DREQ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of , and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
The DMA cycle is started.
Acceptance is resumed after the write cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.)
Idle
Minimum of 2 cycles
[1]
Request
release
Bus
[2]
Read
[3]
Request clear period
Transfer
source
DMA
read
Write
DREQ
DREQ
DREQ Level Activated Normal Mode Transfer
destination
Transfer
DMA
write
Idle
Acceptance resumes
Minimum of 2 cycles
[4]
Request
release
Bus
[5]
Read
[6]
Request clear period
Transfer
DMA
read
source
Write
destination
DMA
Transfer
write
Idle
Acceptance resumes
[7]
release
Bus