E62655RUSB Renesas Electronics America, E62655RUSB Datasheet - Page 447

• Manufacturer Part Number: E62655RUSB
• Description: EMULATOR BASE H8S/2655R W/USB
• Manufacturer: Renesas Electronics America
• Type: Microcontrollerr

Specifications of E62655RUSB

• Contents: E6000 Emulator Unit and 4 Logic Probes
• For Use With/related Products: H8S/2655R
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.13.2
Table 9.23 shows the port F register configuration.
Table 9.23 Port F Registers
Notes: 1. Lower 16 bits of the address.
Port F Data Direction Register (PFDDR)
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2,
4 to 6, and to H'00 in modes 3 and 7. It retains its prior state after a manual reset, and in software
standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain
their output state or become high-impedance when a transition is made to software standby mode.
Name
Port F data direction register
Port F data register
Port F register
Bit
Modes 1, 2, 4 to 6
Initial value
R/W
Modes 3 and 7
Initial value
R/W
Modes 1, 2, 4 to 6
Pin PF
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
Pins PF
BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1
2. Initial value depends on the mode.
Register Configuration
7
2
functions as the output pin when the corresponding PFDDR bit is set to 1, and as an
to PF
:
:
:
:
:
PF7DDR
0
are designated as bus control input/output pins (LCAS, WAIT, BREQO,
W
W
7
1
0
PF6DDR
W
W
6
0
0
Abbreviation
PFDDR
PFDR
PORTF
PF5DDR
W
W
5
0
0
PF4DDR
W
W
4
0
0
R/W
W
R/W
R
Rev. 5.00 Sep 14, 2006 page 417 of 1060
PF3DDR
W
W
3
0
0
Initial Value
H'80/H'00 *
H'00
Undefined
PF2DDR
W
W
2
0
0
6
to PF
2
PF1DDR
Section 9 I/O Ports
REJ09B0331-0500
3
, which are
W
W
1
0
0
Address *
H'FEBE
H'FF6E
H'FF5E
PF0DDR
W
W
0
0
0
1