89C5121-SK1 Atmel, 89C5121-SK1 Datasheet - Page 67

• Manufacturer Part Number: 89C5121-SK1
• Description: KIT SMART CARD FOR AT89C5121
• Manufacturer: Atmel
• Type: Smart Cardr

Specifications of 89C5121-SK1

• Contents: Board
• For Use With/related Products: AT89C5121
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: T89C5121-SK1; T89C5121-SK1

Read/Write Protection
Lock Byte
4164G–SCR–07/06
}
v o i d g e n e r a t e _ c r c _ i n _ f r a m e ( v o i d )
{
t h e C R C o f a l l t h e d a t a s a n d * /
w h i c h i s t h e C R C _ R E F c o n s t . o f t h e B o o t l o a d e r * /
}
***************************************************************************************************
Table 47. Synthesis of Transfer Protection Mechanisms
Notes:
In order to protect the content of the internal EEPROM, a Software Security Byte (SSB)
defines two security levels:
•
•
•
This SSB Byte is located at address 3FFDh.
When the level 2 is set, the command to set level 1 is disabled. The security levels can
only be increased.
Source
MCU
Intern. EEP
MCU
Ext. EEP
c h e c k s u m _ t x = ( U i n t 1 6 ) F F F F h ;
c h e c k s u m _ t x = c o m p u t e _ c r c ( ( U i n t 1 6 ) d a t a _ b y t e ^ c h e c k s u m _ t x ) ^ ( c h e c k s u m _ t x > > 8 ) ;
w r i t e _ f r a m e ( L O W _ B Y T E ( c h e c k s u m ) ) ;
w r i t e _ f r a m e ( H I G H _ B Y T E ( c h e c k s u m ) ) ;
level 0: SSB = 0xFF: Write and Read are allowed
level 1: SSB = 0xFE: Write is disabled
level 2: SSB = 0xFC: Write and Read are disabled
c h e c k s u m = ~ c h e c k s u m _ t x ;
1. The transfer of SSB Byte is also secured by CRC as the CRC is computed on all the
2. If a Bad transfer has occurred in the Internal EEPROM (CRC is bad), as the CRC
16K data.
check is finally done at the end of CRAM programming, application program will NOT
be executed after any Reset.
Target
CRAM
MCU
Intern. EEP
MCU
Check
CRC computed during CRAM Write operation: if error an error code is applied
on P3.7 and Code execution by LJMP000 is not done.
This Read operation is secured by the Write sequence described above
Same protection as in first row above because CRAM is written in sequence
after each page programming of EEP
Same as above as data are transferred to EEP INT and then to CRAM
/ * l o o p w h i c h c o m p u t e f o r e a c h b y t e ( d a t a _ b y t e ) t o l o a d * /
/ * e n d o f l o o p * /
/ * i n i t o f t h e c r c v a r i a b l e * /
/ * i n v e r t s t h e c h e c k s u m , s o t h e c h e c k w i l l c a l c u l a t e
/ * w r i t e s t h e H I G H _ B Y T E * /
/ * w r i t e s t h e L O W _ B Y T E o f t h e C R C f i r s t * /
/ * w i l l f i n d a c o n s t a n t v a l u e = F 0 B 8
A/T8xC5121
67