AD9549/PCBZ Analog Devices Inc, AD9549/PCBZ Datasheet - Page 23

BOARD EVALUATION FOR AD9549

AD9549/PCBZ

Manufacturer Part Number
AD9549/PCBZ
Description
BOARD EVALUATION FOR AD9549
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9549/PCBZ

Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9549
Primary Attributes
2 Inputs, 2 Outputs, VCO
Secondary Attributes
CMOS, HSTL Output Logic, Graphical User Interface
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
The three coefficients are implemented as digital elements,
necessitating quantized values. Determination of the
programmed coefficient values in this context follows.
The quantized α coefficient is composed of three factors, where
α
The boundary values for each are 0 ≤ α
and 0 ≤ α
The magnitude of the quantized β coefficient is composed of
two factors
where β
The boundary values for each are 0 ≤ β
The optimal values of β
The magnitude of the quantized γ coefficient is composed of
two factors.
where γ
The boundary values for each are 0 ≤ γ
The optimal values of γ
0
, α
1
, and α
α
α
α
α
γ
γ
γ
β
β
β
QUANTIZED
1
0
QUANTIZED
1
2
0
QUANTIZED
1
0
0
0
=
=
=
=
=
=
and β
=
and γ
2
max
max
≤ 7. The optimal values of α
max
max
max
max
max
2
are the programmed values for the α coefficient.
1
[
1
, 0
[
are the programmed values for the β coefficient.
[
, 0
, 0
are the programmed values for the γ coefficient.
, 0
, 0
, 0
, 0
=
=
=
min
min
min
min
min
min
min
( )
( )
γ
β
2048
0
0
α
{
{
{
4095
 
 
 
4095
(
4095
(
0
2
0
0
2
, 7
, 7
22
, 7
and γ
and β
(
(
floor
floor
,
floor
γ
β
( )(
1
,
2
ceil
1
,
,
+
+
round
round
α
round
15
15
1
1
1
)
)
 
)
are
)
are
2
log
log
log
log
α
(
(
(
2
2
2
α
2
γ
2
β
)
2048
×
×
4095
4095
4095
×
4095
0
0
0
0
, α
2
2
α
β
γ
2
≤ 4095 and 0 ≤ γ
≤ 4095, 0 ≤ α
≤ 4095 and 0 ≤ β
α
γ
1
1
2
β
α
1
, and α
+
+
15
α
15
1
)
+
+
}
)
11
]
}
15
15
α
]
)
}
2
1
]
are
 
 
11
1
≤ 22,
 
 
1
1
≤ 7.
≤ 7.
Rev. D | Page 23 of 76
The min(), max(), floor(), ceil() and round() functions are
defined as follows:
To demonstrate the wide programmable range of the loop filter
bandwidth, consider the following design example. The system
clock frequency (f
is 19.44 MHz, the DDS output frequency (f
and the required phase margin (Φ) is 45°. f
bandwidth of the phase detector (25 MHz), and f
(8), so the prescaler is not required. Therefore, R = 1 and S = 8 can
be used for the feedforward and feedback dividers, respectively.
Note that if f
such that S/R = f
values. For example, if f
then the optimal choice for S and R is 1944 and 125, respectively.
The open-loop bandwidth range under the defined conditions
spans 9.5 Hz to 257.5 kHz. The wide dynamic range of the loop
filter coefficients allows for programming of any open-loop
bandwidth within this range under these conditions. The
resulting closed-loop bandwidth range under the same
conditions is approximately 12 Hz to 359 kHz.
The resulting loop filter coefficients for the upper loop bandwidth,
along with the necessary programming values, are shown as
follows:
The function min(x
in the list of arguments.
The function max(x
the list of arguments.
The function ceil(x) increases x to the next higher integer
if x is not an integer; otherwise, x is unchanged.
The function floor(x) reduces x to the next lower integer
if x is not an integer; otherwise, x is unchanged.
The function round(x) rounds x to the nearest integer.
α = 4322509.4784981
α
α
α
β = −0.10354689386232
β
β
γ
γ = −0.12499215775201
γ
0
1
2
0
1
0
1
= 2111 (0x83F)
= 22 (0x16)
= 0 (0x00)
= 3393 (0xD41)
= 0 (0x00)
= 4095 (0xFFF)
= 0 (0x00)
DDS
/f
DDS
R
S
is a noninteger, then R and S must be chosen
) is 1 GHz, the input reference frequency (f
/f
R
with S and R both constrained to integer
R
1
1
= 10 MHz and f
, x
, x
2
2
, … x
, … x
n
n
) chooses the smallest value
) chooses the largest value in
DDS
R
DDS
is within the nominal
= 155.52 MHz,
) is 155.52 MHz,
DDS
/f
R
AD9549
is an integer
R
)

Related parts for AD9549/PCBZ