EVAL6730 STMicroelectronics, EVAL6730 Datasheet - Page 5
![EVAL BOARD FOR L6730XX](/photos/9/30/93060/eval6730_sml.jpg)
EVAL6730
Manufacturer Part Number
EVAL6730
Description
EVAL BOARD FOR L6730XX
Manufacturer
STMicroelectronics
Type
Motor / Motion Controllers & Driversr
Datasheets
1.L6730TR.pdf
(52 pages)
2.L6730DTR.pdf
(50 pages)
3.EVAL6730.pdf
(9 pages)
4.EVAL6732.pdf
(43 pages)
Specifications of EVAL6730
Main Purpose
DC/DC, Step Down
Outputs And Type
1, Non-Isolated
Power - Output
66W
Voltage - Output
3.3V
Current - Output
20A
Voltage - Input
4.5 ~ 14V
Regulator Topology
Buck
Frequency - Switching
400kHz
Board Type
Fully Populated
Utilized Ic / Part
L6730
Input Voltage
8 V to 52 V
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
L6208
Other names
497-5501
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
EVAL6730
The over-current-protection limit is set at 15 A but it can be changed by replacing the
resistors R1 and R12 (see OCL and OCH pin).
●
Using the input voltage to supply the controller no power is required at this input. However
the controller can be supplied separately from the power stage through the Vcc input (4.5-
14V) and, in this case, jumper G1 must be left open.
●
An internal LDO provides the power into the device. The input of this stage is the Vcc pin
and the output (5 V) is the V
voltage from V
shorted.
●
This pin can be used as an input or as a test point. If all the jumper G2 pins are shorted, TP1
can be used as a test point of the voltage at the EAREF pin.
If the pins 2 and 3 of G2 are connected together, TP1 can be used as an input to provide an
external reference for the internal error amplifier.
●
This test point is connected to the Tmask pin.
●
This test point is connected to the S/O/U pin.
●
This pin is connected to the synch pin of the controller.
●
This pin is connected to the PGOOD pin of the controller.
●
Different positions of the dip switch correspond to different settings of the multifunction pin
(S/O/U) (CC/O/U).
Table 4.
Vcc-Gndcc:
V
TP1:
TP2:
TP3:
SYNCH:
PWRGD:
DIP SWITCH
UVLO
12 V
12 V
12 V
12 V
5 V
5 V
5 V
5 V
CCDR
:
Dip switch
CCDR
Not latched
Not latched
Not latched
Not latched
Latched
Latched
Latched
Latched
and Gndcc. In this case the pins 1 and 3 of the jumper G1 must be
OVP
CCDR
pin. The LDO can be bypassed, providing directly a 5 V
SINK
Not
Yes
Not
Yes
Not
Yes
Not
Yes
CC
Vsou/ VB
0.2
0.3
0.4
0.5
0.6
0.7
0
1
CCDR
B B B
DIP SWITCH
S1-S7
S2-S7
S3-S7
S4-S7
S5-S7
S6-S7
S7
S1
STATE
Features
G
A
B
C
D
E
H
F
5/9