M5307C3 Freescale Semiconductor, M5307C3 Datasheet - Page 129

• Manufacturer Part Number: M5307C3
• Description: KIT EVALUATION FOR MCF5307
• Manufacturer: Freescale Semiconductor
• Series: ColdFire®r
• Type: Microprocessorr

Specifications of M5307C3

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MCF5307
• Interface Type: Ethernet
• For Use With/related Products: MCF5307
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

MOTOROLA
Taking into account the 1 nS clock advance with 2 nS required for the MCF5307, the 3 nS hold time of the
SDRAM leaves 0 nS timing margin.
Hold times are probably less critical because trace impedances and capacitances on the board will tend to
extend these hold times.
In conclusion, using a zero-delay buffer in the negative one nanosecond model works with PC100 memory,
assuming that the MCF5307 from the 0H55J mask set is used.
1.6 ABEL Code
The following is the ABEL code file for the helper MUX for interfacing between a MCF5307 and standard
168-pin unbuffered SDRAM:
module SDRAMmux
title 'SDRAM Mux Controller for the MCF5307EVM'
"5307mux device 'ispLSI22LV10';
;"*****************************************************"
;"This abel file contains the code to mux the address lines"
;"allowing the MCF5307 to support all 168-pin 1 Bank x 64 bit PC compliant DIMMS"
;"It was targeted to Lattice ispLSI 22LV10 PAL
;"All logic with this PAL is com
;"CS: XXX "
;"*****************************************************"
;"*****************************************************"
;"Declaration Section
•
•
- 7 nS (Clock to valid data for PC100 memory)
+ 1 nS (advance from clock driver)
- 5.5 nS (Valid input to BCLKO falling - setup time (parameter B1))
= 10.5 nS timing margin
-2 nS (Input hold time for MCF5307) (parameter B4)
-1 nS (advance from clock)
= 0 nS timing margin
signals and 0.0 nS for control signals. However, SDRAM control signals are routed through 22 Ohm
series termination resistors, before hitting their nominal 50 pF SDRAM input load. This would
skew these signals by at least 1.0 nS. Because 1.0 nS is required for PC100 memory, this leaves 0.0
nS timing margin, an adequate outcome.
SDRAM-to-MCF5307 setup time for reads:
For the SDRAM-to-MCF5307 hold time:
22 nS (BCLKO period)
3 nS (Output hold time for PC66 and PC100 memory)
Connecting the MCF5307 to 168-Pin Unbuffered SDRAM DIMMs
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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"
// This is 10 nS for PC66 memory
"
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