MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 304

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9.5.1 Basic Transfer Protocol
9.5.2 Single Beat Transfer
9.5.2.1 Single Beat Read Flow
MPC555
USER’S MANUAL
is the responsibility of the system to handle any such clock skew problems that could
occur.
The basic transfer protocol defines the sequence of actions that must occur on the
MPC555 / MPC556 bus to perform a complete bus transaction. A simplified scheme of
the basic transfer protocol is illustrated in
The basic transfer protocol provides for an arbitration phase and an address and data
transfer phase. The address phase specifies the address for the transaction and the
transfer attributes that describe the transaction. The data phase performs the transfer
of data (if any is to be transferred). The data phase may transfer a single beat of data
(4 bytes or less) for nonburst operations, a 4-beat burst of data (4 x 4 bytes), an 8-beat
burst of data (8 x 2 bytes) or a 16-beat burst of data (16 x 1 bytes).
During the data transfer phase, the data is transferred from master to slave (in write
cycles) or from slave to master (on read cycles).
During a write cycle, the master drives the data as soon as it can, but never earlier than
the cycle following the address transfer phase. The master has to take into consider-
ation the “one dead clock cycle” switching between drivers to avoid electrical conten-
tions. The master can stop driving the data bus as soon as it samples the TA line
asserted on the rising edge of the CLKOUT.
During a read cycle, the master accepts the data bus contents as valid at the rising
edge of the CLKOUT in which the TA signal is sampled/asserted.
The basic read cycle begins with a bus arbitration, followed by the address transfer,
then the data transfer. The handshakes are illustrated in the following flow and timing
diagrams as applicable to the fixed transaction protocol.
Arbitration
/
MPC556
Address Transfer
Figure 9-3 Basic Transfer Protocol
EXTERNAL BUS INTERFACE
Rev. 15 October 2000
Figure
Data Transfer
9-3.
Termination
MOTOROLA
9-8