MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 36
MPC555CME
Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet
1.MPC555CME.pdf
(966 pages)
Specifications of MPC555CME
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Number
E-7
E-8
G-1
G-2
G-3
G-4
G-5
G-6
G-7
G-8
G-9
G-10
G-11
G-12
G-13
G-14
G-15
G-16
G-17
G-18
G-19
G-20
G-21
G-22
G-23
G-24
G-25
G-26
G-27
G-28
G-29
G-30
G-31
G-32
G-33
G-34
G-35
G-36
G-37
G-38
G-39
MPC555 / MPC555
USER’S MANUAL
Figure
LC Filter Example (Alternative) ...................................................................... E-7
PLL Off-Chip Capacitor Example ................................................................... E-7
CLKOUT Timing .......................................................................................... G-16
External Clock Timing ................................................................................. G-23
Synchronous Output Signals Timing ........................................................... G-24
Synchronous Active Pull-Up and Open Drain Outputs Signals Timing ....... G-25
Synchronous Input Signals Timing .............................................................. G-26
Input Data Timing in Normal Case .............................................................. G-27
External Bus Read Timing (GPCM Controlled — ACS = ‘00’) .................... G-28
External Bus Read Timing (GPCM Controlled — TRLX = ‘0’ ACS = ‘10’) .. G-29
External Bus Read Timing (GPCM Controlled — TRLX = ‘0’ ACS = ‘11’) .. G-30
External Bus Read Timing
(GPCM Controlled — TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’) ......................... G-31
Address Show Cycle Bus Timing ................................................................ G-32
Address and Data Show Cycle Bus Timing ................................................. G-33
External Bus Write Timing (GPCM Controlled — TRLX = ‘0’, CSNT = ‘0’) . G-34
External Bus Write Timing (GPCM Controlled — TRLX = ‘0’, CSNT = ‘1’) . G-35
External Bus Write Timing (GPCM Controlled — TRLX = ‘1’, CSNT = ‘1’) . G-36
External Master Read from Internal Registers Timing ................................ G-37
External Master Write to Internal Registers Timing ..................................... G-38
Interrupt Detection Timing for External Level Sensitive Lines ..................... G-39
Interrupt Detection Timing for External Edge Sensitive Lines ..................... G-40
Debug Port Clock Input Timing ................................................................... G-41
Debug Port Timings ..................................................................................... G-42
Reset Timing — Configuration from Data Bus ............................................ G-44
Reset Timing — Data Bus Weak Drive During Configuration ..................... G-45
Reset Timing — Debug Port Configuration ................................................. G-46
JTAG Test Clock Input Timing .................................................................... G-48
JTAG — Test Access Port Timing Diagram ................................................ G-49
JTAG — TRST Timing Diagram .................................................................. G-50
Boundary Scan (JTAG) Timing Diagram ..................................................... G-51
QSPI Timing — Master, CPHA = 0 ............................................................. G-55
QSPI Timing — Master, CPHA = 1 ............................................................. G-55
QSPI Timing — Slave, CPHA = 0 ............................................................... G-56
QSPI Timing — Slave, CPHA = 1 ............................................................... G-56
TPU3 Timing ............................................................................................... G-58
MCPSM Enable to vs_pclk Pulse Timing Diagram ..................................... G-59
MPWMSM Minimum Output Pulse Example Timing Diagram .................... G-60
MCPSM Enable to MPWMO Output Pin
Rising Edge Timing Diagram ....................................................................... G-61
MPWMSM Enable to MPWMO Output Pin
Rising Edge Timing Diagram ....................................................................... G-61
MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge
Timing Diagram ........................................................................................... G-62
MMCSM Minimum Input Pin (Either Load or Clock)
Rev. 15 October 2000
LIST OF FIGURES
MOTOROLA
Number
Page
xxxvi
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