MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 429

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

13.10.2 Queue Boundary Conditions
MPC555
USER’S MANUAL
When the QADC64 encounters a CCW with the pause bit set, the queue enters the
paused state after completing the conversion specified in the CCW with the pause bit.
The pause flag is set and a pause software interrupt may optionally be issued. The sta-
tus of the queue is shown to be paused, indicating completion of a sub-queue. The
QADC64 then waits for another trigger event to again begin execution of the next sub-
queue.
The following are queue operation boundary conditions:
Boundary conditions also exist for combinations of pause and end-of-queue. One case
is when a pause bit is in one CCW and an end-of-queue condition is in the next CCW.
The conversion specified by the CCW with the pause bit set completes normally. The
pause flag is set. However, since the end-of-queue condition is recognized, the com-
pletion flag is also set and the queue status becomes idle, not paused. Examples of
this situation include:
• The first CCW in a queue contains channel 63, the end-of-queue (EOQ) code.
• BQ2 (beginning of queue 2) is set at the end of the CCW table (63) and a trigger
• BQ2 is set to CCW0 and a trigger event occurs on queue 1. After reading CCW0,
• BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64 - 127)
• The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6
• The pause bit is set in CCW63
• During queue 1 operation, the pause bit is set in CCW14 and BQ2 points to
/
The queue becomes active and the first CCW is read. The end-of-queue is rec-
ognized, the completion flag is set, and the queue becomes idle. A conversion is
not performed.
event occurs on queue 2.
BQ2. The end-of-queue condition is recognized, a conversion is performed, the
completion flag is set, and the queue becomes idle.
the end-of-queue condition is recognized, the completion flag is set, and the
queue becomes idle. A conversion is not performed.
and a trigger event occurs on queue 2. Refer to 7.6.3 Control Register two for in-
formation on BQ2. The end-of-queue condition is recognized immediately, the
completion flag is set, and the queue becomes idle. A conversion is not per-
formed.
CCW15
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in the QADC64 behavior. For example,
if BQ2 is set to CCW0, CCW0 contains the EOQ code, and a trigger
event occurs on queue 1, the QADC64 reads CCW0 and detects
both end-of-queue conditions. The completion flag is set for queue 1
only and it becomes idle.
Rev. 15 October 2000
13.12.8 QADC64 Control Register 2 (QACR2)
NOTE
MOTOROLA
13-17
on