MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 44
MPC555CME
Manufacturer Part Number
MPC555CME
Description
KIT EVALUATION FOR MPC555
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Datasheet
1.MPC555CME.pdf
(966 pages)
Specifications of MPC555CME
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC555
Data Bus Width
32 bit
Interface Type
RS-232
For Use With/related Products
MPC555
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Page
Table
Number
Number
16-10 TouCAN Register Map................................................................................... 16-21
16-11 TCNMCR Bit Descriptions ............................................................................ 16-23
16-12 CANICR Bit Descriptions .............................................................................. 16-25
16-13 CANCTRL0 Bit Descriptions......................................................................... 16-25
16-14 RX MODE[1:0] Configuration......................................................................... 16-26
16-15 Transmit Pin Configuration ............................................................................ 16-26
16-16 CANCTRL1 Bit Descriptions.......................................................................... 16-27
16-17 PRESDIV Bit Descriptions ............................................................................ 16-28
16-18 CANCTRL2 Bit Descriptions......................................................................... 16-28
16-19 TIMER Bit Descriptions................................................................................. 16-29
16-20 RXGMSKHI, RXGMSKLO Bit Descriptions .................................................. 16-30
16-21 ESTAT Bit Descriptions ................................................................................ 16-31
16-22 Transmit Bit Error Status ............................................................................... 16-32
16-23 Fault Confinement State Encoding ................................................................ 16-32
16-24 IMASK Bit Descriptions................................................................................. 16-32
16-25 IFLAG Bit Descriptions ................................................................................. 16-33
16-26 RXECTR, TXECTR Bit Descriptions............................................................. 16-33
17-1 Enhanced TCR1 Prescaler Divide Values ........................................................ 17-6
17-2 TCR1 Prescaler Values ..................................................................................... 17-6
17-3 TCR2 Counter Clock Source ............................................................................. 17-7
17-4 TCR2 Prescaler Control..................................................................................... 17-8
17-5 TPU3 Register Map ........................................................................................... 17-9
17-6 TPUMCR Bit Descriptions .............................................................................. 17-11
17-7 DSCR Bit Descriptions.................................................................................... 17-13
17-8 DSSR Bit Descriptions.................................................................................... 17-14
17-9 TICR Bit Descriptions ..................................................................................... 17-15
17-10 CIER Bit Descriptions ................................................................................... 17-15
17-11 CFSRx Bit Descriptions ................................................................................ 17-16
17-12 HSQRx Bit Descriptions................................................................................ 17-17
17-13 HSSRx Bit Descriptions ................................................................................ 17-18
17-14 CPRx Bit Descriptions .................................................................................. 17-18
17-15 Channel Priorities .......................................................................................... 17-19
17-16 CISR Bit Descriptions ................................................................................... 17-19
17-17 TPUMCR2 Bit Descriptions .......................................................................... 17-20
17-18 Entry Table Bank Location............................................................................. 17-21
17-19 IMB Clock Frequency/Minimum Guaranteed Detected Pulse ....................... 17-21
17-20 TPUMCR3 Bit Descriptions .......................................................................... 17-21
17-21 Parameter RAM Address Offset Map ............................................................ 17-22
18-1 DPTRAM Register Map ..................................................................................... 18-3
18-2 DPTMCR Bit Descriptions ................................................................................ 18-4
18-3 RAMBAR Bit Descriptions ................................................................................ 18-5
19-1 CMF Register Programmer’s Model .................................................................. 19-5
19-2 CMFMCR Bit Descriptions................................................................................. 19-6
MPC555 / MPC556
LIST OF TABLES
MOTOROLA
USER’S MANUAL
Rev. 15 October 2000
xliv
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