MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 443

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

13.11.2 Interrupt Register
13.11.3 Interrupt Levels and Time Multiplexing
13.12 Programming Model
MPC555
USER’S MANUAL
The QADC64 interrupt register QADC64INT specifies the priority level of QADC64 in-
terrupt requests
The values contained in the IRL1 and IRL2 fields in QADC64INT determine the priority
of QADC64 interrupt service requests.The interrupt levels for queue 1 and queue 2
may be different.
The QADC64 conditionally generates interrupts to the bus master via the IMB IRQ sig-
nals. When the QADC64 sets a status bit assigned to generate an interrupt, the
QADC64 drives the IRQ bus. The value driven onto IRQ[7:0] represents the interrupt
level assigned to the interrupt source. Under the control of ILBS, each interrupt request
level is driven during the time multiplexed bus during one of four different time slots,
with eight levels communicated per time slot. No hardware priority is assigned to inter-
rupts. Furthermore, if more than one source on a module requests an interrupt at the
same level, the system software must assign a priority to each source requesting at
that level.
Each QADC64 occupies 1 Kbyte (512 16-bit entries) of address space. The address
space consists of ten 16-bit control, status, and port registers; 64 16-bit entries in the
CCW table; and 64 16-bit entries in the result table. The result table occupies 192 16-
bit address locations because the result data is readable in three data alignment for-
mats.
Table 13-6
register name represents “A” or “B” for the QADC64_A or QADC64_B module, respec-
tively. The address offset shown is from the base address of the module. Refer to
MPC555 / MPC556 Address Map
MPC556 memory map.
ILBS [1:0]
IMB3 CLOCK
IMB3 IRQ [7:0]
/
MPC556 QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE-64
Figure 13-11
shows the QADC64 memory map. The lowercase “x” appended to each
Figure 13-11 Interrupt Levels on IRQ with ILBS
00
displays the interrupt levels on IRQ with ILBS.
01
IRQ
0:7
Rev. 15 October 2000
10
IRQ
8:15
to locate each QADC64 module in the MPC555 /
11
16:23
IRQ
24:31
00
IRQ
01
IRQ
0:7
10
11
MOTOROLA
13-31
1.3