74lvc2g86 NXP Semiconductors, 74lvc2g86 Datasheet

no-image

74lvc2g86

Manufacturer Part Number
74lvc2g86
Description
Dual 2-input Exclusive-or Gate
Manufacturer
NXP Semiconductors
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74lvc2g86DC
Manufacturer:
NXP
Quantity:
3 000
Part Number:
74lvc2g86DP
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
74lvc2g86GT
Manufacturer:
NXPLIPS
Quantity:
25 000
1. General description
2. Features
The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial Power-down applications using I
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
74LVC2G86
Dual 2-input EXCLUSIVE-OR gate
Rev. 05 — 7 September 2007
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
ESD protection:
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
24 mA output drive (V
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CC
= 3.0 V)
Product data sheet
OFF
. The I
OFF

Related parts for 74lvc2g86

74lvc2g86 Summary of contents

Page 1

... Dual 2-input EXCLUSIVE-OR gate Rev. 05 — 7 September 2007 1. General description The 74LVC2G86 provides a dual 2-input EXCLUSIVE-OR gate. Inputs can be driven from either 3 devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using I circuitry disables the output, preventing the damaging backfl ...

Page 2

... Temperature range Name 74LVC2G86DP +125 C 74LVC2G86DC +125 C 74LVC2G86GT +125 C 74LVC2G86GM +125 C 4. Marking Table 2. Marking Type number 74LVC2G86DP 74LVC2G86DC 74LVC2G86GT 74LVC2G86GM 5. Functional diagram mna737 Fig 1. Logic symbol Fig 3. Logic diagram (one driver) 74LVC2G86_5 ...

Page 3

... Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate 74LVC2G86 terminal 1 index area Transparent top view Description data input data input data output ground (0 V) data input data input data output supply voltage © ...

Page 4

... CC O Active mode Power-down mode +125 C amb derates linearly with 2.5 mW/K. tot derates linearly with 8.0 mW/K. tot derates linearly with 2.4 mW/K. tot Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Output Min Max Unit 0.5 +6 [1] 0.5 +6 ...

Page 5

... GND 5 5 Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Min Typ Max Unit 1. +125 ...

Page 6

... GND 1. 5 per pin 3.3 V and amb Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate [1] Min Typ Max - 0 500 - 2 ...

Page 7

... C and V = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively. amb where nA, nB input M GND t PHL output Table 9. Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate + +125 C [1] Min Typ Max Min 1.4 3.8 9.9 1.4 0.8 2.5 5.7 0.8 0.8 3.0 5.7 0.8 0.8 2.3 4.7 0.8 0.6 1.9 3.6 0 ...

Page 8

... DUT the pulse generator. o Load Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Output 1.5 V 1 EXT mna616 V EXT PLH ...

Page 9

... Product data sheet 2.5 scale (1) ( 0.38 0.18 3.1 3.1 0.65 0.22 0.08 2.9 2.9 REFERENCES JEDEC JEITA - - - Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate detail 4.1 0.47 0.5 0.2 0.13 0.1 3.9 0.33 EUROPEAN PROJECTION SOT505 ...

Page 10

... Product data sheet 2.5 scale (1) ( 0.27 0.23 2.1 2.4 0.5 0.17 0.08 1.9 2.2 REFERENCES JEDEC JEITA MO-187 Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate detail 3.2 0.40 0.21 0.4 0.2 0.13 3.0 0.15 0.19 EUROPEAN PROJECTION SOT765 ...

Page 11

... scale 1.05 0.35 0.40 0.6 0.5 0.95 0.27 0.32 REFERENCES JEDEC JEITA - - - MO-252 Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate 4 ( EUROPEAN PROJECTION © NXP B.V. 2007. All rights reserved. SOT833-1 ISSUE DATE 04-07-22 04-11- ...

Page 12

... 1.65 0.35 0.15 0.55 0.5 0.1 1.55 0.25 0.05 REFERENCES JEDEC JEITA MO-255 - - - Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate detail 0.05 0.05 0.05 EUROPEAN PROJECTION SOT902 ISSUE DATE 05-11-16 05-11-25 © NXP B.V. 2007. All rights reserved. ...

Page 13

... Product data sheet - Product data sheet - Product specification - Product specification - Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate Supersedes 74LVC2G86_4 74LVC2G86_3 74LVC2G86_2 74LVC2G86_1 - © NXP B.V. 2007. All rights reserved ...

Page 14

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com Rev. 05 — 7 September 2007 74LVC2G86 Dual 2-input EXCLUSIVE-OR gate © NXP B.V. 2007. All rights reserved ...

Page 15

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All rights reserved. Date of release: 7 September 2007 Document identifier: 74LVC2G86_5 ...

Related keywords