74LVT373 PHILIPS [NXP Semiconductors], 74LVT373 Datasheet

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74LVT373

Manufacturer Part Number
74LVT373
Description
3.3 Volt ABT octal transparent latch 3-State
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet

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Philips Semiconductors Low Voltage Products
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
PIN DESCRIPTION
July 1993
20–Pin Plastic SOL
20–Pin Plastic SSOP
20–Pin Plastic TSSOP
Designed for use in the 3.3V
high–performance market
Supports mixed–mode signal operation; 5V
input and output voltages with 3.3V V
Bus–hold inputs eliminate the need for
external pull-up resistors to hold unused
pins
Live insertion/extraction permitted
No bus current loading when output is tied
to 5V bus
8–bit transparent latch
3-State output buffers
Zero-static power dissipation
Pin and function compatibility with ABT
AC and DC performance compatibility with
ABT
3.3 Volt ABT octal transparent latch (3–State)
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
SYMBOL
C
I
t
t
C
PLH
PHL
CCZ
OUT
PIN NUMBER
IN
PACKAGES
11
10
20
1
Propagation delay
Dn to Qn
Input capacitance
Output capacitance
Total supply current
PARAMETER
SYMBOL
CC
Q0-Q7
D0-D7
GND
V
TEMPERATURE RANGE
OE
E
CC
-40 C to +85 C
-40 C to +85 C
-40 C to +85 C
DESCRIPTION
The 74LVT373 device is designed specifically
for low–voltage (3.3V) V
provide a TTL interface to a 5V system
environment.
The 74LVT373 high-performance BiCMOS
device combines zero static and low dynamic
power dissipation with high speed and high
output drive.
The 74LVT373 device is an octal transparent
latch coupled to eight 3-State output buffers.
The two sections of the device are controlled
Latch–up protection exceeds 500mA per
JEDEC JC40.2 Std 17
ESD protection exceeds 2000 V per MIL
STD 883 Method 3015 and 200 V per
Machine Model
Output enable input (active-Low)
Data inputs
Data outputs
Enable input (active-High)
Ground (0V)
Positive supply voltage
C
V
V
Outputs disabled; V
I
I
L
= 0V or V
= 0V or V
= 50pF; V
2
CC
T
operation, but can
CC
CC
amb
CC
CONDITIONS
= 5V
= 25 C; GND = 0V
ORDER CODE
CC
74LVT373PW
74LVT373DB
74LVT373D
=5.5V
FUNCTION
independently by Enable (E) and Output
Enable (OE) control gates.
The data on the D inputs are transferred to
the latch outputs when the Latch Enable (E)
input is High. The latch remains transparent
to the data inputs while E is High, and stores
the data that is present one setup time before
the High-to-Low enable transition.
The 3-State output buffers are designed to
drive heavily loaded 3-State buses, MOS
memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all
eight 3-State buffers independent of the latch
operation.
When OE is Low, the latched or transparent
data appears at the outputs. When OE is
High, the outputs are in the High-impedance
”OFF” state, which means they will neither
drive nor load the bus.
TYPICAL
DRAWING NUMBER
Objective specification
4.2
50
4
7
74LVT373
0172D
1640B
TBD
UNIT
pF
pF
ns
A

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74LVT373 Summary of contents

Page 1

... The 74LVT373 high-performance BiCMOS device combines zero static and low dynamic power dissipation with high speed and high output drive. The 74LVT373 device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled CONDITIONS ...

Page 2

... OPERATING MODE Q0 – Enable and read register H L Latch and read register H NC Hold Z Disable outputs Objective specification 74LVT373 ...

Page 3

... Input transition rise or fall rate T Operating free-air temperature range amb July 1993 CONDITIONS V < < output in Off or High state output in Low state PARAMETER 4 Objective specification 74LVT373 RATING UNIT –0.5 to +4.6 V –18 mA –1.2 to +5.5 V –50 mA –0 –65 to 150 C ...

Page 4

... 3.6V; One input at V -0.6V Other inputs GND CC V 1.2V 0. GND OE/ Objective specification 74LVT373 LIMITS Temp = - +85 C UNIT 1 MIN TYP MAX –1 -0.2 CC 2.4 V 2.0 0.2 0.5 0.4 V 0.5 0. ...

Page 5

... Waveform 3. Data Setup and Hold Times OE V –0. Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 6 Objective specification 74LVT373 LIMITS V = 2.7V UNIT CC 1 MAX MAX PLH PHL ...

Page 6

... Termination resistance should be equal pulse generators. July 1993 6V 90% NEGATIVE V OPEN PULSE R L GND POSITIVE V PULSE 10% FAMILY Amplitude 74LVT V (Min OUT 7 Objective specification 74LVT373 t AMP ( 10% 10 THL F TLH TLH R THL F ...

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