74LVTH373 FAIRCHILD [Fairchild Semiconductor], 74LVTH373 Datasheet

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74LVTH373

Manufacturer Part Number
74LVTH373
Description
Low Voltage Octal Transparent Latch with 3-STATE Outputs
Manufacturer
FAIRCHILD [Fairchild Semiconductor]
Datasheet
©1999 Fairchild Semiconductor Corporation
74LVT373, 74LVTH373 Rev. 1.5.0
74LVT373, 74LVTH373
Low Voltage Octal Transparent Latch with 3-STATE Outputs
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
74LVT373WM
74LVT373SJ
74LVT373MTC
74LVTH373WM
74LVTH373SJ
74LVTH373MTC
Order Number
Input and output interface capability to systems at
5V V
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH373),
also available without bushold feature (74LVT373)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32 mA/+64 mA
Functionally compatible with the 74 series 373
ESD performance:
– Human-body model
– Machine model
– Charged-device model
All packages are lead free per JEDEC: J-STD-020B standard.
CC
Package
200V
Number
MTC20
MTC20
M20D
M20D
M20B
M20B
2000V
1000V
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
General Description
The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfy-
ing the input timing requirements is latched. Data
appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH, the bus output is in a high
impedance state.
The LVTH373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal latches are designed for low-voltage (3.3V)
V
interface to a 5V environment. The LVT373 and
LVTH373 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining low power dissipation.
CC
Package Description
applications, but with the capability to provide a TTL
February 2008
www.fairchildsemi.com

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74LVTH373 Summary of contents

Page 1

... Features Input and output interface capability to systems Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH373), also available without bushold feature (74LVT373) Live insertion/extraction permitted Power Up/Down high impedance provides glitch-free bus loading Outputs source/sink –32 mA/+64 mA ...

Page 2

... When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 Logic Symbols Truth Table LE X inputs enters the ...

Page 3

... Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 3 www.fairchildsemi.com ...

Page 4

... Symbol V Supply Voltage CC V Input Voltage I I HIGH-Level Output Current OH I LOW-Level Output Current OL T Free-Air Operating Temperature Input Edge Rate, V ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 Parameter (1) GND I GND Parameter 0.8V–2.0V Rating –0.5V to +4.6V –0.5V to +7.0V – ...

Page 5

... Notes: 2. All typical values are Applies to bushold versions only (74LVTH373 external driver must source at least the specified current to switch from LOW-to-HIGH external driver must sink at least the specified current to switch from HIGH-to-LOW. 6. This is the increase in supply current for each input that is at the specified voltage level rather than V © ...

Page 6

... Hold Time Note: 9. All typical values are (10) Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT Note: 10. Capacitance is measured at frequency f ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 (7) Conditions V (V) C 50pF (8) 3.3 (8) 3 3.3V ±0.3V CC (9) Min ...

Page 7

... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 13.00 12.60 A 11.43 ...

Page 8

... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 8 www.fairchildsemi.com ...

Page 9

... Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 9 www.fairchildsemi.com ...

Page 10

... Datasheet Identification Product Status Advance Information Formative or In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production ©1999 Fairchild Semiconductor Corporation 74LVT373, 74LVTH373 Rev. 1.5.0 PDP-SPM™ FPS™ ® Power220 FRFET SM POWEREDGE Global Power Resource Power-SPM™ Green FPS™ ...

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