AD2S83 Analog Devices, Inc., AD2S83 Datasheet
AD2S83
Available stocks
Related parts for AD2S83
AD2S83 Summary of contents
Page 1
... Resolution Set by User. Two control pins are used to select the resolution of the AD2S83 to be 10, 12 bits allow- ing optimum resolution for each application. Ratiometric Tracking Conversion. This technique provides continuous output position data without conversion delay ...
Page 2
... VELOCITY SIGNAL LINEARITY AD2S83AP 0 kHz–500 kHz 0.5 MHz–1 MHz AD2S83IP 0 kHz–500 kHz 0.5 MHz–1 MHz Reversion Error AD2S83AP AD2S83IP 5 DC Zero Offset Gain Scaling Accuracy Output Voltage Dynamic Ripple INPUT/OUTPUT PROTECTION Analog Inputs Analog Outputs DIGITAL POSITION Resolution ...
Page 3
... NOTES 1 Angular accuracy is not guaranteed <50 Hz reference frequency. 2 Linearity derates from 500 kHz–1000 kHz @ 0.0017%/kHz. 3 Refer to Definition of Linearity, “The AD2S83 as a Silicon Tachogenerator.” 4 Worst case reversion error at temperature extremes. 5 Velocity output offset dependent on value for R6. 6 Refer to timing diagram. ...
Page 4
... Current ± ± ± All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Specifications subject to change without notice. Model AD2S83AP AD2S83IP ( 5 Conditions DB1–DB16 Only ± ...
Page 5
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD2S83 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 6
... CONVERTER RESOLUTION 0.164795 9.88770 Two major areas of the AD2S83 specification can be selected by 0.082397 4.94385 the user to optimize the total system performance. The resolu- tion of the digital output is set by the logic state of the inputs SC1 and SC2 to be 10, 12 bits; and the dynamic char- acteristics of bandwidth and tracking rate are selected by the and – ...
Page 7
... The amplitude of the reference signal applied to the converter’s input is not critical, but care should be taken to ensure it is kept within the recommended operating limits. The AD2S83 will not be damaged if the reference is supplied to the converter without the power supplies and/or the signal inputs. ...
Page 8
... The components should be connected as shown in Figure 1. Free PC compatible software is available to help users select the optimum component values for the AD2S83, and display the transfer gain, phase and small step response. For more detailed information and explanation, see the Circuit Functions and Dynamic Performance section ...
Page 9
... DB9 to DB16 (with the ENABLE input taken to a logic “LO”) regardless of the state of the BYTE SELECT pin. Note that when the AD2S83 is used with a resolution less than 16 bits the unused data lines are pulled to a logic “LO.” A logic “HI” on the BYTE SELECT input will present the eight most significant data bits on data output DB1 and DB8. A logic “ ...
Page 10
... AD2S83 RIPPLE CLOCK INHIBIT INHIBIT ENABLE SELECT Parameter BUSY DATA DIR ...
Page 11
... S Strobing DATA LOAD and COMPLEMENT pins to logic LO will set the logic HI bits of the AD2S83 counter state. Those bits of the applied data which are logic LO will not change the corresponding bits in the AD2S83 counter. For Example: ...
Page 12
... The AC ERROR OUTPUT may be fed to the PSD via a simple ac coupling network (R2, C1) to remove any dc offset at this point. Note, however, that the PSD of the AD2S83 is a wide- band demodulator and is capable of aliasing HF noise down to within the loop bandwidth. This is most likely to happen where ...
Page 13
... The normalized gain and phase diagrams are given in Figures 5 and –3 –6 –9 –12 0 103.7 kΩ 180 135 –45 –90 –135 –180 0.0 = µ 129 A = Ω – 5. –2 AD2S83 0.04 0.1 0.2 0.4 1 FREQUENCY – 0.04 0.1 0.2 0.4 1 FREQUENCY – ...
Page 14
... THE AD2S83 AS A SILICON TACHOGENERATOR Position Control Using the AD2S83 The AD2S83 has been optimized for use as a feedback device for velocity as well as position. A traditional position control loop shown below compares a demand position with an actual to derive a position error and hence a velocity demand. ...
Page 15
... The tachogenerator was connected at the nondrive end of the motor shaft with the resolver located behind the drive shaft of the motor. The AD2S83 was located remotely. The AD2S83 was set up with a 200 Hz bandwidth, reference fre- quency of 2.6 kHz and resolution of 14 bits. The comparative analysis can be summarized: ...
Page 16
... The phase shift is normally induced through the connections from the resolver to the converter. Maintaining equal lengths of screened twisted pair cable from the resolver to the AD2S83 will reduce the effects of resistive imbalance, and therefore, reduce differential phase shift. 3.0 LSB Update Ripple LSB update noise occurs as the resolver rotates and the digital outputs of the RDC are updated ...
Page 17
... The limiting factor in the measuring of low or “creep” speeds is the level of dc offset present at zero velocity. The zero velocity dc offset at the output of the AD2S83 is a function of the input bias current to the VCO and the value for the input resistor R6. See “Circuit Functions and Dynamic Performance VCO.” ...
Page 18
... AC ERROR output as Sin ωt sin (θ–φ) or the DEMOD output as sin (θ–φ). To use the AD2S83 in this mode refer to the “Control Transformer” application note. OTHER PRODUCT AD2S90 ...
Page 19
... Plastic Leaded Chip Carrier (PLCC) (P-44A) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.048 (1.21) 0.042 (1.07) 0.042 (1.07) 0.048 (1.21 0.042 (1.07 PIN 1 IDENTIFIER TOP VIEW (PINS DOWN 0.020 0.656 (16.66) (0.50 0.650 (16.51) 0.110 (2.79) 0.695 (17.65) 0.085 (2.16) SQ 0.685 (17.40) AD2S83 0.025 (0.63) 0.015 (0.38) 0.050 0.63 (16.00) (1.27) BSC 0.59 (14.99) 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.040 (1.01) 0.025 (0.64) ...