CY23EP09 Cypress Semiconductor, CY23EP09 Datasheet

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CY23EP09

Manufacturer Part Number
CY23EP09
Description
9-Output Zero Delay Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07760 Rev. *B
Features
REF
• 10 MHz to 220 MHz maximum operating range
• Zero input-output propagation delay, adjustable by
• Multiple low-skew outputs
• 25 ps typical cycle-to-cycle jitter
• 15 ps typical period jitter
• Standard and High drive strength options
• Available in space-saving 16-pin 150-mil SOIC or
• 3.3V or 2.5V operation
• Industrial temperature available
Block Diagram
loading on CLKOUT pin
— 45 ps typical output-output skew
— One input drives nine outputs, grouped as 4 + 4 + 1
4.4-mm TSSOP packages
S2
S1
PLL
Select Input
Decoding
2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output
MUX
198 Champion Court
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Functional Description
The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed
to distribute high-speed clocks and is available in a 16-pin
SOIC or TSSOP package. The -1H version operates up to 220
(200) MHz frequencies at 3.3V (2.5V), and has higher drive
than the -1 devices. All parts have on-chip PLLs that lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
There are two banks of four outputs each, which can be
controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The PLL enters a power-down mode when there are no rising
edges on the REF input (less than ~2 MHz). In this state, the
outputs are three-stated and the PLL is turned off, resulting in
less than 25 µA of current draw.
In the special case when S2:S1 is 1:0, the PLL is bypassed
and REF is output from DC to the maximum allowable
frequency. The part behaves like a non-zero delay buffer in this
mode, and the outputs are not tri-stated.
The CY23EP09 is available in different configurations, as
shown in the Ordering Information table. The CY23EP09-1 is
the base part. The CY23EP09-1H is the high-drive version of
the -1, and its rise and fall times are much faster than the -1.
These parts are not intended for 5V input-tolerant applications
CLKA1
CLKA2
CLKB1
CLKB2
San Jose
GND
Pin Configuration
REF
V
S2
DD
,
1
2
3
4
5
6
7
8
Top View
CA 95134-1709
Zero Delay Buffer
15
14
13
12
11
10
16
9
Revised October 5, 2005
www.DataSheet4U.com
CLKOUT
CLKA4
CLKA3
V
GND
CLKB4
CLKB3
S1
DD
CY23EP09
408-943-2600

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CY23EP09 Summary of contents

Page 1

... S1 Cypress Semiconductor Corporation Document #: 38-07760 Rev. *B Functional Description The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The -1H version operates up to 220 (200) MHz frequencies at 3.3V (2.5V), and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin ...

Page 2

... Buffered clock output, Bank B Ground 3.3V or 2.5V supply Buffered clock output, Bank A Buffered clock output, Bank A Buffered output, internal feedback on this pin [4] CLOCK B1–B4 CLKOUT Three-state Driven Three-state Driven Driven Driven Driven Driven CY23EP09 www.DataSheet4U.com Output Source PLL Shutdown PLL N PLL N Reference Y PLL N Page ...

Page 3

... V < (standard drive (High drive –8 mA (standard drive –12 mA (High drive) OH REF = 0 MHz (Industrial) Unloaded outputs, 66-MHz REF CY23EP09 www.DataSheet4U.com Min. Max. Unit 3.0 3.6 V 2.3 2 °C –40 85 °C – – – ...

Page 4

... All outputs equally loaded, 2.5V supply high drive PLL Bypass mode PLL enabled @ 3.3V PLL enabled @2.5V Measured at V /2. DD Any output to any output, 3.3V supply Measured at V /2. DD Any output to any output, 2.5V supply in Operating Conditions Table. L CY23EP09 www.DataSheet4U.com Min. Max. Unit 2.3 2.7 V – 0 µ ...

Page 5

... S2:S1 = 1:0 mode, 3.3V, <15pF, high drive S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive S2:S1 = 1:0 mode, 2.5V, <15pF, high drive Duty Cycle Timing All Outputs Rise/Fall Time 2.0V(1.8V) 2.0V(1.8V) 0.8V(0.6V CY23EP09 www.DataSheet4U.com Min. Typ. Max. – – 1.0 – – 65 125 – 53 100 – – – ...

Page 6

... Any output, Part Test Circuits Test Circuit # 0.1 µ F OUTPUTS V DD 0.1 µ F GND GND Document #: 38-07760 Rev. *B Output-Output Skew Input-Output Propagation Delay Part-Part Skew CLK C LOAD CY23EP09 www.DataSheet4U.com Page ...

Page 7

... CLKOUT and CLKA/CLKB. Data is shown for 66 MHz. Delay is a weak function of frequency. Document #: 38-07760 Rev. *B -20 -10 0 Load Load C LK A/B (pF) 0 -20 -10 0 Load CLKOUT- Load CLKA/B (pF) CY23EP09 www.DataSheet4U.com S tandard D rive H igh D rive 10 20 Standard Drive High Drive 10 20 Page ...

Page 8

... Document #: 38-07760 Rev. *B 100 133 166 Frequency (MHz) 100 133 Frequency (MHz) CY23EP09 www.DataSheet4U.com 15pF, -45C, Standard Drive 15pF, 90C, Standard Drive 30pF, -45C, Standard Drive 30pF, 90C, Standard Drive 15pF, -45C, High Drive 15pF, 90C, High Drive 30pF, -45C, High Drive ...

Page 9

... CY23EP09 www.DataSheet4U.com riv riv riv riv e ...

Page 10

... High Drive 2.5V, High Drive 1.E+03 1.E+03 1.E+04 1.E+04 1.E+05 1.E+05 Offset Frequency (Hz) Offset Frequency (Hz) 3.3V, Standard Drive 3.3V, Standard Drive 2.5V, Standard Drive 2.5V, Standard Drive 1.E+03 1.E+03 1.E+04 1.E+04 1.E+05 1.E+05 Offset Frequency (Hz) Offset Frequency (Hz) CY23EP09 www.DataSheet4U.com 3.3V, Standard Drive 3.3V, Standard Drive 3.3V, High Drive 3.3V, High Drive 1.E+06 1.E+06 1.E+07 1.E+07 1.E+08 1.E+08 2.5V, High Drive 2.5V, High Drive 3.3V, High Drive 3.3V, High Drive 1.E+06 1.E+06 1.E+07 1.E+07 1.E+08 1.E+08 and Drive Strength ...

Page 11

... SOIC – Tape and Reel CY23EP09SXI-1H 16-pin 150-mil SOIC CY23EP09SXI-1HT 16-pin 150-mil SOIC – Tape and Reel CY23EP09ZXC-1H 16-pin 4.4-mm TSSOP CY23EP09ZXC-1HT 16-pin 4.4-mm TSSOP – Tape and Reel CY23EP09ZXI-1H 16-pin 4.4-mm TSSOP CY23EP09ZXI-1HT 16-pin 4.4-mm TSSOP – Tape and Reel Package Drawing and Dimensions ...

Page 12

... DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 6.25[0.246] PACKAGE WEIGHT 0.05 gms 6.50[0.256] Z16.173 ZZ16.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY23EP09 www.DataSheet4U.com MAX. PART # STANDARD PKG. 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] 51-85091-*A Page ...

Page 13

... Document History Page Document Title: CY23EP09 2.5V or 3.3V, 10-220-MHz, Low Jitter, 9-Output Zero Delay Buffer Document Number: 38-07760 REV. ECN NO. Issue Date ** 345446 See ECN *A 355777 See ECN *B 401036 See ECN Document #: 38-07760 Rev. *B Orig. of Change Description of Change RGL New data sheet RGL ...

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