CY2510 Cypress Semiconductor Corporation., CY2510 Datasheet
CY2510
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CY2510 Summary of contents
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... Well suited to both 100- and 133-MHz designs • Ten (CY2509) or eleven (CY2510) LVCMOS/LVTTL outputs • Single output enable pin for CY2510 version, dual pins on CY2509 devices allow shutting down a portion of the outputs • 3.3V power supply • On board 25 damping resistors • ...
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Pin Definitions Pin Pin No. Pin No. Name (2509) (2510) CLK 24 24 FBIN 16, 17, 9, 15, 16, 20 n/a 21 FBOUT 12 ...
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Spread Aware™ Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we de- signed this product so as not to ...
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... Jitter, Cycle-to-Cycle JC Ordering Information Ordering Code CY2509ZC-1 CY2510ZC-1 Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Longer input rise and fall time will degrade skew and jitter performance. ...
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Package Diagram 24-Pin Thin Shrink Small Outline Package (TSSOP) Document #: 38-07230 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any ...
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Document Title: CY2509/10 Spread Aware™, Ten/Eleven Output Zero Delay Buffer Document Number: 38-07230 Issue REV. ECN NO. Date ** 110495 01/07/02 *A 122844 12/14/02 Document #: 38-07230 Rev. *A Orig. of Change SZV Change from Spec number: 38-00914 to 38-07230 ...