cy28323 Cypress Semiconductor Corporation., cy28323 Datasheet
cy28323
Available stocks
Related parts for cy28323
cy28323 Summary of contents
Page 1
... PCI4 PCI0:6 PCI5 PCI6 VDD_PCI VTT_PWRGD# VDD_48MHz 48MHz RST# GND_48MHz *FS0/48MHz 24_48MHz *FS1/24_48MHz VDD_48MHz RST# • 3901 North First Street • San Jose CY28323 4 CPU and Chipsets PCI REF 48M 24_48M [[1 REF0/MULTSEL0 GND_REF 3 46 VDD_CPU ...
Page 2
... This pin also serves as a power-on strap option to determine device operating frequency as described in Table 4. This output will be used as the reference clock for USB host controller in Intel 845 (Brookdale) platforms. For Intel Brookdale - G platforms, this output will be used as the VCH reference clock. CY28323 Page [+] Feedback ...
Page 3
... PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. G Ground Connection: Connect all ground pins to the common system ground plane. P 3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Con- nect to 3.3V. G Analog Ground Connection: Ground for core logic, PLL circuitry. CY28323 Page [+] Feedback ...
Page 4
... Rr = 475 1 5*Iref OH IREF = 2. 475 1 6*Iref OH IREF = 2. 475 1 6*Iref OH IREF = 2. 475 1 7*Iref OH IREF = 2. 475 1 7*Iref OH IREF = 2.32 mA CY28323 1. 1. 1.25V @ 1.75V @ 50 2. 0.47V @ 50 0.56V @ 60 0.58V @ 0.84V @ 60 0.81V @ 50 0.97V @ 60 Page [+] Feedback ...
Page 5
... Acknowledge from slave 30:37 Byte count from slave – 8 bits 38 Acknowledge 39:46 Data byte from slave – 8 bits 47 Acknowledge 48:55 Data byte from slave – 8 bits 56 Acknowledge ... Data bytes from slave/Acknowledge ... Data byte N from slave – 8 bits ... Not Acknowledge ... Stop CY28323 Page [+] Feedback ...
Page 6
... Reserved ‘010’ = Reserved ‘011’ = Reserved ‘100’ = ±0.25% ‘101’ = –0.5% ‘110’ = ±0.5% ‘111’ = ±0.38% SW Frequency selection bits. See Table 4. Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) CY28323 Power On Default Power On Default 1 ...
Page 7
... HW control; IREF multiplier is determined by MULTSEL[0:1] input pins control; IREF multiplier is determined by Byte[4], Bit[5:6]. IREF multiplier 00 = Ioh IREF 01 = Ioh IREF 10 = Ioh IREF 11 = Ioh IREF Reserved Reserved Reserved Reserved Reserved CY28323 Power On Default Power On Default ...
Page 8
... Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read-only. Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read-only. Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read-only. Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28323 Power On Default Power On ...
Page 9
... Watchdog timer time-out occurs. Under re- covery frequency mode, CY28323 will not respond to any attempt to change output frequency via the SMBus control bytes. System software can unlock CY28323 from its re- covery frequency mode by clearing the WD_EN bit. Reserved CY28323 ...
Page 10
... Pin Description ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog Timer time-out occurs. The clock generator will automatically switch to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL From latched FS[4: From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0] CY28323 Power On Default ...
Page 11
... CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used. When it is set, the frequency ratio stated in the SEL[4:0] register will be used. Pin Description Reserved Reserved Reserved Reserved Reserved Reserved CY28323 Power On Default Power On ...
Page 12
... Reserved. Write with “1” Reserved. Write with “1” Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CY28323 Power On Default 1 1 Power On Default Power On Default ...
Page 13
... CY28323 PLL Gear Constants PCI (G) 34.0 48.00741 35.0 48.00741 36.0 48.00741 37.0 48.00741 38.0 48.00741 39.0 48.00741 40.0 48.00741 41.0 48.00741 31.5 48.00741 32.5 48.00741 34.0 48.00741 35.0 48.00741 36.0 48.00741 37.0 48.00741 38.0 48.00741 39.0 48.00741 40.0 48.00741 41.0 48.00741 33.3 48.00741 34.0 48.00741 35.0 48.00741 36 ...
Page 14
... Watchdog timer before they attempt to make a frequency change. If the system hangs and a Watchdog Timer time-out occurs, a system reset will be gen- erated and a recovery frequency will be activated. All the related registers are summarized in Table 5. Description CY28323 Page [+] Feedback ...
Page 15
... M-Value Register and select the CPU output frequency by changing the value of the N-Value Register. Fixed Value for Range of N-Value Register M-Value Register for Different CPU Frequency 93 45 CY28323 97–255 127–245 Page [+] Feedback ...
Page 16
... V < For I = 6*IRef Configuration OH REF, 48 MHz 3V66, PCI REF, 48MHz 3V66, PCI, Three-state /V = 3.465V 133 MHz DD_CORE DD33 CPU 3.465V DD_CORE VDDQ3 CY28323 Min. Max. Unit 3.135 3.465 22 14.318 14.318 MHz Min. Max. Unit /2 2.0 ...
Page 17
... Measured with test loads Measured with test loads Measured with test loads Measured with test loads Measured with test loads = 2.5V, duty cycle is measured at 1.25V Where rising edge and intersecting falling edge CY28323 Min. Max. Unit 175 700 ps oh 0.5 2.0 V/ns 1 ...
Page 18
... Ended Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew 3V66 3V66 t 5 Document #: 38-07004 Rev CY28323 Page [+] Feedback ...
Page 19
... Clock Skew 3V66 PCI t 7 CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK Ordering Information Ordering Code CY28323PVC 48-pin Small Shrunk Outline Package (SSOP) Document #: 38-07004 Rev Package Type Commercial CY28323 Operating Range Page [+] Feedback ...
Page 20
... 0.005 =VIA to respective supply plane layer CY28323 0.1 F Page [+] Feedback ...
Page 21
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28323 51-85061-C ...
Page 22
... PRELIMINARY Document Title: CY28323 FTG For Intel Pentium 4 CPU and Chipsets Document Number: 38-07004 Issue Orig. of REV. ECN NO. Date Change ** 106090 06/27/01 IKA *A 110677 11/15/01 IKA *B 122712 12/14/02 RBI Document #: 38-07004 Rev. *B Description of Change New Data Sheet Revised 2nd bullet on page 1 (add “845” to first Brookdale, Bookdale-G to Brookdale-G) Added power up requirements to operating conditions information ...