CY2833 CYPRESS [Cypress Semiconductor], CY2833 Datasheet
CY2833
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CY2833 Summary of contents
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... GND_3V66 16 33 VDD_48 MHz 17 GND_48 MHz 32 66BUFF0/3V66_2 66BUFF1/3V66_3 18 3V66_1/VCH 31 66BUFF2/3V66_4 19 30 PCI_STOP# 66IN/3V66_5 3V66_0 20 29 PD# 28 VDD_3V66 21 VDD_CORE 27 22 GND_3V66 26 SCLK GND_CORE 23 VTT_PWRGD# 25 SDATA 24 , • San Jose CA 95134 • 408-943-2600 Revised June 25, 2004 CY28339 USB/ DOT 48M 48M 48M 48M TCLK/2 ...
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... sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. SMBus-compatible SDATA. SMBus-compatible SCLK. 3.3V power supply for outputs. 3.3V power supply for 48 MHz. 3.3V power supply for phase-locked loop (PLL). Ground for outputs. Ground for PLL. CY28339 Description [2] Page ...
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... Although the data (bits) in the command is considered “don’t care,” it must be sent and will be acknowledged. After the Command Code and the Byte Count have been acknowl- edged, the sequence (Byte 0, Byte 1, and Byte 2) described below will be valid and acknowledged. Description Description CY28339 Page ...
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... Control MSB. 66IN to 66M delay Control LSB. Reserved. Set = 0. DOT_48M Edge Rate Control. When set to 1, the edge is slowed by 15%. Reserved. Set = 0. USB_48M edge rate control. When set to 1, the edge is slowed by 15%. CY28339 Description Description Page ...
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... All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. R and N register mux selection and N values come from the ROM data is loaded from DAF (SMBus) registers. CY28339 Description Description Description Description ...
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... HIGH-to-LOW transition, except the CPUT clock. The +0.37, –0.37 CPU clocks are held with the CPUT clock pin driven HIGH with +0.50, –1.50 a value of 2 × Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down. CY28339 Page ...
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... Figure 3. Power-down Assertion Timing Waveforms Figure – Buffered Mode Document #: 38-07507 Rev. *A CY28339 Page ...
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... There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to (Mult 0 “select”) × (Iref), and the CPUC signal will not be driven. Due to external pull-down circuitry CPUC will be LOW during this stopped state. CY28339 Page ...
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... LOW, the stoppable PCI clocks will be stopped in a logic LOW state. Reading SMBus Byte 0,Bit 3 will return a 0 value if either of these control bits are set LOW (which indicates that the devices stoppable PCI clocks are not running). CY28339 ) (see setup Page ...
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... Operation VTT_PWRGD# = toggle The various output current configurations are shown in the host swing select functions table. For all configurations, the deviation from the expected output current is ±7% as shown in the current accuracy table. CY28339 Device is not affected, VTT_PWRGD# is ignored. State Sample Inputs straps Wait for < ...
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... The measurements were taken at 1.5V. 3V66 to PCI Un-Buffered Clock Skew Figure 1 shows the timing relationship between 3V66_0 and PCI(0:2,4:8) and PCIF when configured to run in the unbuf- fered mode. Figure 12. 66IN to 66BUFF(0:2) Output Delay Figure CY28339 Output Current Voh @ Z Ioh = 6*Iref 1. Ioh = 6*Iref 0. ...
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... Series resistance in the buffer circuit – Ros (see Figure Current accuracy at given configuration into nominal test load for given configuration. Iout 0V Figure 14. Buffer Characteristics Min. 3000 Ω (recommended) N/A Max Load CY28339 Slope ~ 1/R 0 1.2V Vout Max. N/A 1.2V Units Page ...
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... average over 1 µ s duration CPU at 0.7V Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point Measured at crossing point V OX CY28339 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD –65 150 ° ...
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... Measured at crossing point V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V 66BUFF Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V PCI /PCIF Measurement at 1.5V Measured at crossing point V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V CY28339 Min. Max. 175 700 -T )/( – – 125 – ...
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... PCIF clock’s rising edge. When crystal meets min. 40 Ω device series resis- tance specification 475Ω .4Ω 63.4 Ω Figure 15. 1.0V Test Load Termination CY28339 Min. Max. – 250 45 55 20.83 20.83 0.5 1.0 – ...
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... Tr Tf Figure 17. For Single-ended Output Signals Package Type 48-pin TSSOP 48-pin TSSOP – Tape and Reel 48-pin TSSOP 48-pin TSSOP – Tape and Reel CY28339 Measurement Point 2pF Measurement Point 2pF Output under Test Probe Load Cap - Product Flow Commercial, 0 ° ° C Commercial, 0 ° ...
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... GAUGE PLANE MAX. 0.25[0.010] 0.20[0.008] 0.051[0.002] 0.152[0.006] 0.170[0.006] SEATING 0.279[0.011] PLANE CY28339 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 0.508[0.020] 0.762[0.030] 0°-8° ...
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... Document History Page Document Title: CY28339 Intel CK408 Mobile Clock Synthesizer Document Number: 38-07507 Issue REV. ECN NO. Date ** 122362 12/13/02 *A 237868 See ECN Document #: 38-07507 Rev. *A Orig. of Change RGL New Data Sheet RGL Added Lead Free Devices CY28339 Description of Change Page ...