DS25MB100EVK National Semiconductor, DS25MB100EVK Datasheet
DS25MB100EVK
Specifications of DS25MB100EVK
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DS25MB100EVK Summary of contents
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... All driver outputs are internally terminated with 50Ω Functional Block Diagram Note: All CML inputs and outputs must be AC coupled for optimal performance. © 2009 National Semiconductor Corporation DS25MB100 Features ■ 2:1 multiplexer and 1:2 buffer ■ 0.25–2.5 Gbps fully differential data paths ■ ...
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Simplified Block Diagram www.national.com 2 20208902 ...
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Pin Descriptions Pin Name Pin Number I/O LINE SIDE HIGH SPEED DIFFERENTIAL IO's IN Inverting and non-inverting differential inputs at the line side. IN+ and IN− have an internal 50Ω IN− 34 connected to an internal reference voltage. ...
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Connection Diagram Functional Description The DS25MB100 is a signal conditioning 2:1 multiplexer and a 1:2 buffer designed to support port redundancy up to 2.5 Gbps. The high speed inputs are self-biased to about 1.3V and are designed for AC coupling. ...
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Pre-Emphasis Level in mV DEL_[1:0] PP (VODB 1300 0 1 1300 1 0 1300 1 1 1300 (default) TABLE 4. Switch-Side Pre-Emphasis Controls Pre-Emphasis DES_[1:0] Level (VODB 1300 0 1 1300 1 0 ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CML Input/Output Voltage Junction Temperature Storage Temperature Lead Temperature Soldering, 4 seconds Thermal Resistance, θ (Note 8) JA Thermal Resistance, θ ...
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Symbol Parameter T Pre-Emphasis Width Tested at −9 dB Pre-emphasis level, DEx[1:0]=11 PE x=S for switch side Pre-emphasis control x=L for line side Pre-emphasis control See Figure 4 on measurement condition. R Output Termination (Note On-chip termination from OUT+ or ...
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Note 4: K28.7 pattern is a 10-bit repeating pattern of K28.7 code group {001111 1000} K28.5 pattern is a 20-bit repeating pattern of +K28.5 and −K28.5 code groups {110000 0101 001111 1010} Note 5: Device output random jitter is a ...
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FIGURE 4. Test Condition for Output Pre-Emphasis Duration FIGURE 5. AC Test Circuit FIGURE 6. Receiver Input Termination and Bias Circuit 9 20208950 20208907 20208908 www.national.com ...
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Application Information www.national.com FIGURE 7. Application Diagram 10 20208909 ...
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FIGURE 8. Network Switch System With Redundancy 11 20208910 www.national.com ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted LLP-36 Package Order Number DS25MB100TSQ NS Package Number SQA36A 12 ...
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Notes 13 www.national.com ...
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