gtlp1b151 Fairchild Semiconductor, gtlp1b151 Datasheet

gtlp1b151

Manufacturer Part Number

gtlp1b151

Description

1-bit Lvttl/gtlp Transceiver With Separate Lvttl Port And Feedback Path

Manufacturer

Fairchild Semiconductor

Datasheet

1.GTLP1B151.pdf (7 pages)

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GTLP1B151M

GTLP1B151MX

GTLP1B151K8X

GTLP1B151

1-Bit LVTTL/GTLP Transceiver

with Separate LVTTL Port and Feedback Path

General Description

The GTLP1B151 is a 1-bit transceiver that provides

LVTTL-to-GTLP signal level translation. Individual LVTTL

and GTLP driver enables are also available. The

GTLP1B151 offers separate LVTTL inputs and outputs,

and can provide a feedback path for control and diagnos-

tics monitoring.

High-speed backplane operation is a direct result of

GTLP’s reduced output swing ( 1V), reduced input thresh-

old levels and output edge rate control. The edge rate

Semiconductor derivative of the Gunning Transistor Logic

(GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-rate control and is pro-

cess, voltage and temperature compensated. GTLP’s I/O

structure is similar to GTL and BTL but offers different out-

put levels and receiver threshold. Typical GTLP output volt-

age levels are: V

Ordering Code:

control minimizes bus-settling time. GTLP is a Fairchild

Order Number

Package Number

0.5V, V

(Preliminary)

MAB08A

M08A

1.5V, and V

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TUBE]

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TAPE and REEL]

8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

[TAPE and REEL]

REF

DS500484

1V.

Features

Separate LVTTL inputs and outputs

A feedback path for control and diagnostics monitoring

Bidirectional interface between GTLP and LVTTL logic

levels

Designed with edge rate control circuitry to reduce out-

put noise on the GTLP port

receiver threshold adjustibility

Special PVT compensation circuitry to provide consis-

tent performance over variations of process, supply volt-

age and temperature

TTL compatible driver and control inputs

Designed using Fairchild advanced BiCMOS technology

Bushold data inputs on A port to eliminate the need for

external pull-up resistors for unused inputs

Power up/down and power off high impedance for live

insertion

Open drain on GTLP to support wired-or connection

Flow through pinout optimizes PCB layout

A Port source/sink 24mA / 24mA

B Port sink 50mA

REF

Package Description

pin provides external supply reference voltage for

June 2001

Revised February 2002

www.fairchildsemi.com

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gtlp1b151 Summary of contents

Page 1

... LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path General Description The GTLP1B151 is a 1-bit transceiver that provides LVTTL-to-GTLP signal level translation. Individual LVTTL and GTLP driver enables are also available. The GTLP1B151 offers separate LVTTL inputs and outputs, and can provide a feedback path for control and diagnos- tics monitoring ...

Page 2

... C C Port LVTTL Output Functional Description The GTLP1B151 is a 1-bit transceiver that supports GTLP and LVTTL signal levels. Data polarity is non-inverting with sep- arate LVTTL inputs and outputs and there are individual GTLP and LVTTL output enable controls. Functional Tables Inputs ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 2) DC Output Sink Current into C Port Output Source Current from ...

Page 4

DC Electrical Characteristics Symbol Test Conditions I All Ports 1.5V PU/ Ports V 3.45V Port GND ...

Page 5

Test Circuits and Timing Waveforms Test Circuit for C Outputs Test OPEN PLH PHL PLZ PZL t /t GND PHZ PZH Note: C includes probes and Jig capacitance. L Voltage Waveforms Propagation Delay V ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow www.fairchildsemi.com Package Number M08A 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...

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