ics8531-01 Integrated Device Technology, ics8531-01 Datasheet

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ics8531-01

Manufacturer Part Number
ics8531-01
Description
Differential Input Lvpecl Output 1 9 500-mhz Fanout Buffer
Manufacturer
Integrated Device Technology
Datasheet
B
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-
3.3V LVPECL FANOUT BUFFER
G
CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or
SSTL input levels. The clock enable is internally synchronized
to eliminate runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output skew and part-to-part skew character-
istics make the ICS8531-01 ideal for high performance work-
station and server applications.
IDT
HiPerClockS™
IC S
LOCK
CLK_SEL
ENERAL
CLK_EN
nPCLK
/ ICS
PCLK
nCLK
CLK
1-TO-9, 3.3V LVPECL FANOUT BUFFER
D
The ICS8531-01 is a low skew, high performance
1-to-9 Differential-to-3.3V LVPECL Fanout Buffe
Perfor mance Clock Solutions from IDT. The
ICS8531-01 has two selectable clock inputs. The
and a member of the HiPerClockS™ family of High
IAGRAM
D
0
1
ESCRIPTION
D
LE
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
1
P
F
• Nine differential 3.3V LVPECL outputs
• Selectable differential CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential
• PCLK, nPCLK supports the following input types:
• Maximum output frequency: 500MHz
• Translates any single ended input signal (LVCMOS, LVTTL,
• Additive phase jitter, RMS: 0.17ps (typical)
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
• Industrial Temperature information available upon request
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
LVPECL, CML, SSTL
GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
packages
EATURES
IN
A
CLK_SEL
SSIGNMENT
CLK_EN
nPCLK
PCLK
nCLK
CLK
V
V
CC
7mm x 7mm x 1.4mm package body
EE
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
32-Lead LQFP
ICS8531-01
Y package
Top View
ICS8531AY-01 REV. F APRIL 11, 2007
ICS8531-01
24
23
22
21
20
19
18
17
V
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
CCO
CCO

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ics8531-01 Summary of contents

Page 1

... SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output skew and part-to-part skew character- istics make the ICS8531-01 ideal for high performance work- station and server applications ...

Page 2

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ABLE IN ESCRIPTIONS ...

Page 3

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER T 3A ABLE ONTROL NPUT UNCTION ...

Page 4

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs Continuous Current 50mA Surge Current 100mA Package Thermal Impedance, θ JA Storage Temperature, T -65°C to 150°C STG T 4A ABLE OWER ...

Page 5

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER T 4D. LVPECL DC C ABLE HARACTERISTICS ...

Page 6

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications ...

Page 7

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER P ARAMETER CCO LVPECL V EE -1.3V ± 0.165V 3. UTPUT OAD EST IRCUIT nQx Qx nQy Qy tsk( UTPUT KEW 80% Clock 20% Outputs UTPUT ISE ALL IME nCLK0, nCLK1 CLK0, CLK1 nQ0:nQ4 ...

Page 8

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER IRING THE IFFERENTIAL NPUT TO Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio ...

Page 9

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER IFFERENTIAL LOCK NPUT NTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING V and V input requirements. Figures show interface PP CMR examples for the HiPerClockS CLK/nCLK input driven by the most common driver types ...

Page 10

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING V input requirements. Figures show interface CMR examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested 3 ...

Page 11

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER T LVPECL O ERMINATION FOR UTPUTS The clock layout topology shown below is a typical termina- tion for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs ...

Page 12

... Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8531-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. ...

Page 13

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. F IGURE T o calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage ...

Page 14

... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8531-01 is: 632 IDT ™ / ICS ™ 1-TO-9, 3.3V LVPECL FANOUT BUFFER R ...

Page 15

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ACKAGE UTLINE AND IMENSIONS ABLE Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS ™ 1-TO-9, 3.3V LVPECL FANOUT BUFFER 32 L LQFP UFFIX FOR EAD D ACKAGE IMENSIONS ...

Page 16

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ABLE RDERING NFORMATION ...

Page 17

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER ...

Page 18

... ICS8531-01 LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...

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