ics85411 Integrated Device Technology, ics85411 Datasheet
ics85411
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ics85411 Summary of contents
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... LOW SKEW, 1-TO-2 DIFFERENTIAL-TO- LVDS FANOUT BUFFER G D ENERAL ESCRIPTION The ICS85411 is a low skew, high performance IC S 1-to-2 Differential-to-LVDS Fanout Buffer and a HiPerClockS™ member of the HiPerClock S™ family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential in- put levels ...
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... ICS85411AM REV. C JANUARY 17, 2007 ...
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... ICS85411AM REV. C JANUARY 17, 2007 µ A µ A µ A µ µ ...
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... ICS85411AM REV. C JANUARY 17, 2007 ...
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... FFSET ROM ARRIER REQUENCY meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment 200MHz (12kHz to 20MHz) = 0.05ps typical 10M 100M 500M ( ICS85411AM REV. C JANUARY 17, 2007 ...
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... UTPUT Clock Outputs O UTPUT DC Input x 100% D IFFERENTIAL 6 I NFORMATION V Cross Points NPUT EVEL tsk(o) S KEW 80% 80% 20 ISE ALL IME V DD LVDS 100 UTPUT OLTAGE ETUP ICS85411AM REV. C JANUARY 17, 2007 V CMR V OD 20% out out ...
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... IDT ™ / ICS ™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER out out OWER V out Input I OSB out D IFFERENTIAL 7 LVDS EAKAGE ETUP DD LVDS UTPUT HORT IRCUIT URRENT ICS85411AM REV. C JANUARY 17, 2007 OFF out I OSD out ETUP ...
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... For example, if the input DD clock swing is only 2.5V and V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input V_REF C1 0. INGLE NDED IGNAL RIVING P UTPUT INS 8 = 3.3V, V_REF should be 1.25V DD CLK nCLK D I IFFERENTIAL NPUT ICS85411AM REV. C JANUARY 17, 2007 ...
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... Ohm nCLK HiPerClockS LVPECL Input 2B CLK/nCLK LOCK NPUT 3.3V LVPECL D RIVER Ohm LVDS_Driv er R1 100 Ohm 2D CLK/nCLK LOCK NPUT 3.3V LVDS D RIVER ICS85411AM REV. C JANUARY 17, 2007 D RIVEN BY 3.3V CLK nCLK Receiv er D RIVEN BY ...
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... DIFFERENTIAL-TO-LVDS FANOUT BUFFER receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used recommended to terminate across near the the unused outputs. LVDS R1 100 100 Ohm Differential Transmission Line LVDS D IGURE YPICAL RIVER 10 3. ERMINATION ICS85411AM REV. C JANUARY 17, 2007 ...
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... This section provides information on power dissipation and junction temperature for the ICS85411. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85411 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V Power (core) ...
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... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS85411 is: 636 IDT ™ / ICS ™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER R ...
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... ° 0 Reference Document: JEDEC Publication 95, MS-012 ° 8 ICS85411AM REV. C JANUARY 17, 2007 ...
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... ICS85411AM REV. C JANUARY 17, 2007 ° ° ° ° ...
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... ICS85411AM REV. C JANUARY 17, 2007 ...
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... ICS85411 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) © ...