ICS87004 ICST [Integrated Circuit Systems], ICS87004 Datasheet
ICS87004
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ICS87004 Summary of contents
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... Internal bias on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL. The ICS87004 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The refer- ...
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... www.icst.com/products/hiperclocks.html 2 ICS87004 - -LVCMOS/LVTTL IFFERENTIAL ERO ELAY LOCK ENERATOR ...
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... www.icst.com/products/hiperclocks.html 3 ICS87004 - -LVCMOS/LVTTL ERO ELAY LOCK ENERATOR ...
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... www.icst.com/products/hiperclocks.html 4 ICS87004 - -LVCMOS/LVTTL IFFERENTIAL ERO ELAY LOCK ENERATOR 70° ...
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... 2.5V±5 0°C DD DDA DDO www.icst.com/products/hiperclocks.html 5 ICS87004 - -LVCMOS/LVTTL IFFERENTIAL ERO ELAY LOCK ENERATOR 2.5V±5 0°C 70° ...
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... www.icst.com/products/hiperclocks.html 6 ICS87004 - -LVCMOS/LVTTL IFFERENTIAL ERO ELAY LOCK ENERATOR 70° ...
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... LVCMOS GND -1.25V±5% 2.5V O UTPUT Qx V CMR UTPUT KEW V DDO 2 20% t ➤ cycle n+1 Clock Outputs t cycle n UTPUT ISE www.icst.com/products/hiperclocks.html 7 ICS87004 - -LVCMOS/LVTTL IFFERENTIAL ERO ELAY LOCK ENERATOR I NFORMATION SCOPE OAD EST IRCUIT V DDO 2 V DDO 2 t sk(o) ...
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... UTPUT UTY YCLE ULSE IDTH ERIOD 87004AG 1:4, D IFFERENTIAL nCLK0 nCLK1 V OL CLK0, CLK1 DDO 2 V Q0: the average mean P D ROPAGATION V DDO 2 www.icst.com/products/hiperclocks.html 8 ICS87004 - -LVCMOS/LVTTL ERO ELAY LOCK ENERATOR V DDO ELAY REV. A JUNE 16, 2004 ...
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... UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS87004 provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal PLL. V should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin ...
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... HiPerClockS Input D F 3B. H NPUT RIVEN BY IGURE RIVER 3.3V 3.3V LVDS_Driv er CLK nCLK HiPerClockS Input 3D. H NPUT RIVEN BY IGURE www.icst.com/products/hiperclocks.html 10 ICS87004 - -LVCMOS/LVTTL IFFERENTIAL ERO ELAY LOCK ENERATOR 3. Ohm CLK Ohm nCLK HiPerClockS Input ...
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... LOW ABLE FOR JA Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS87004 is: 2578 87004AG 1: ELIABILITY NFORMATION 24 L TSSOP EAD ...
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... ° www.icst.com/products/hiperclocks.html 12 ICS87004 - -LVCMOS/LVTTL ERO ELAY LOCK ENERATOR ...
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... " " " www.icst.com/products/hiperclocks.html 13 ICS87004 - -LVCMOS/LVTTL ERO ELAY LOCK ENERATOR ° ...
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... " www.icst.com/products/hiperclocks.html 14 ICS87004 - -LVCMOS/LVTTL IFFERENTIAL ERO ELAY LOCK ENERATOR " REV. A JUNE 16, 2004 ...