ics97ulp877b Integrated Device Technology, ics97ulp877b Datasheet

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ics97ulp877b

Manufacturer Part Number
ics97ulp877b
Description
1.8v Low-power Wide-range Frequency Clock Driver
Manufacturer
Integrated Device Technology
Datasheet

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Part Number:
ics97ulp877bH
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ics97ulp877bHLF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ics97ulp877bHLFT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ics97ulp877bHT
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
ics97ulp877bKLF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Recommended Application:
Product Description/Features:
Switching Characteristics:
Block Diagram
CLK_INC
0981C—04/05/05
CLK_INT
1.8V Low-Power Wide-Range Frequency Clock Driver
FB_INC
FB_INT
10K-100k
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866/
SSTUA32864/SSTUA32866/SSTUA32S868/
SSTUA32S865/SSTUA32S869
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Auto PD when input signal is at a certain logic state
Period jitter: 40ps (DDR2-400/533)
Half-period jitter: 60ps (DDR2-400/533)
OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
CYCLE - CYCLE jitter 40ps
AV
OE
OS
DD
GND
30ps (DDR2-667/800)
Integrated
Circuit
Systems, Inc.
50ps (DDR2-667/800)
Powerdown
Control and
Test Logic
PLL
LD*
PLL bypass
LD* or OE
LD*, OS or OE
30ps (DDR2-667/800)
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
C
D
G
H
A
B
E
F
J
K
CLK_INT
CLK_INC
CLKC1
CLKC2
CLKC3
CLKT1
CLKT2
CLKT3
AGND
AVDD
CLK_INC
CLK_INT
1
CLKC2
CLKT2
VDDQ
VDDQ
AGND
VDDQ
AVDD
GND
Pin Configuration
C
D
G
H
A
B
E
K
F
J
CLKC4
CLKT0
VDDQ
VDDQ
VDDQ
VDDQ
10
GND
GND
GND
GND
1
2
1
52-Ball BGA
40
11
ICS97ULP877B
2
Top View
CLKC0
CLKT4
VDDQ
VDDQ
40-Pin MLF
GND
GND
NB
NB
NB
NB
3
3
ICS97ULP877B
4
CLKC5
CLKT9
VDDQ
VDDQ
GND
GND
NB
NB
NB
NB
5
4
6
CLKC9
CLKT5
VDDQ
VDDQ
GND
GND
GND
GND
OS
OE
20
31
5
30
21
FB_OUTC
FB_OUTT
FB_INT
FB_INC
CLKC7
CLKT7
VDDQ
FB_INT
FB_INC
FB_OUTC
FB_OUTT
VDDQ
OE
OS
CLKT6
CLKC6
CLKC7
CLKT7
CLKT8
CLKC8
6

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ics97ulp877b Summary of contents

Page 1

... GND K CLKC3 CLKC4 CLKT4 CLKT9 CLKT0 CLKC0 CLKT1 40 CLKC1 CLKT2 VDDQ 1 CLKC2 CLKC2 CLKT3 CLKT2 CLKC3 CLK_INT CLKT4 CLK_INC CLKC4 ICS97ULP877B VDDQ CLKT5 AGND CLKC5 AVDD CLKT6 VDDQ CLKC6 GND 10 CLKT7 CLKC7 11 CLKT8 CLKC8 CLKT9 CLKC9 40-Pin MLF FB_OUTT FB_OUTC ...

Page 2

... FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time t The PLL in ICS97ULP877B clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ...

Page 3

... limit. ODL 3 ICS97ULP877B ...

Page 4

... ICS97ULP877B Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD -0.5V to 2.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0. Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...

Page 5

... CONDITIONS , A VDD CLK_INT, CLK_INC, FB_INC, FB_INT IL OE, OS CLK_INT, CLK_INC, FB_INC, FB_INT IH OE CLK_INT, CLK_INC, FB_INC, FB_INT CLK_INT, CLK_INC, FB_INC, FB_INT ICS97ULP877B MIN TYP MAX 1.7 1.8 1.9 0. DDQ 0. DDQ 0. DDQ 0. DDQ -0 0.3 DDQ 0 0.4 DDQ ...

Page 6

... ICS97ULP877B Timing Requirements 70°C Supply Voltage AVDD, VDDQ = 1 0.1V (unless otherwise stated) A PARAMETER Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization NOTE: The PLL must be able to handle spread spectrum induced skew. NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters ...

Page 7

... OE to any output dis t jit (per) jit(hper) Input Clock SLr1(i) Output Enable (OE), (OS) SLr1(o) t jit(cc+) t jit(cc-) t (Ø)dyn 2 t SPO ∑ (su) ∑ t (h) t skew 7 ICS97ULP877B (MHz) MIN TYP MAX 4.73 8 160 to 410 5.82 8 160 to 270 -40 40 271 to 410 -30 30 -60 60 160 to 270 271 to 410 - 2.5 4 ...

Page 8

... ICS97ULP877B VDD/2 ICS97ULP877B -VDD FB_OUTC FB_OUTT X 0981C—04/05/05 Parameter Measurement Information V DD ICS97ULP877B GND Figure 1. IBIS Model Output Load GND R = 10Ω 0Ω 2.97" 120Ω 10Ω 60Ω 2.97" GND Figure 2. Output Load Test Circuit t c(n) t jit(cc c(n) ± ...

Page 9

... Y , FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0981C—04/05/05 Parameter Measurement Information large number of samples) Figure 4. Static Phase Offset t (skew) Figure 5. Output Skew t C( (jit_per) c( Figure 6. Period Jitter 9 ICS97ULP877B n+1 ...

Page 10

... ICS97ULP877B Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0981C—04/05/05 Parameter Measurement Information t jit(hper_n) t jit(hper_n+ jit(hper) jit(hper_n) 2xf O Figure 7. Half-Period Jitter 80% t slr t slf Figure 8. Input and Output Slew Rates 10 80 20% ...

Page 11

... CK CK FBIN FBIN t ( )dyn Figure 10. Time delay between OE and Clock Output (Y, Y) 0981C—04/05/ SSC OFF SSC )dyn Figure 9. Dynamic Phase Offset 50% VDDQ t en 50% VDDQ ICS97ULP877B SSC OFF SSC )dyn ( )dyn Y Y 50% VDDQ t dis ...

Page 12

... ICS97ULP877B - Place the 2200pF capacitor close to the PLL. - Use a wide trace for the PLL analog power & ground. Connect PLL & caps to AGND trace & connect trace to one GND via (farthest from PLL). - Recommended bead: Fair-Rite P/N 2506036017Y0 or equivalent (0.8 Ohm DC max, 600 Ohms @ 100 MHz). ...

Page 13

... C ----- BALL GRID ----- Max. HORIZ VERT TOTAL d Min/Max 0.35/0. BGA ICS = Standard Device 13 ICS97ULP877B Numeric Designations Numeric Designations for Horizontal Grid for Horizontal Grid Alpha Designations Alpha Designations for Vertical Grid for Vertical Grid (Letters & S (Letters & ...

Page 14

... Top View D THERMALLY ENHANCED, VERY THIN, FINE PITCH BASIC D2 M IN. / MAX IN. / MAX. L MIN. / MAX. Source R eference: MLF2™ SE 10-0053 Ordering Information ICS97ULP877BKLF-T Example: ICS XXXX y K LF- T 0981C—04/05/05 Seating Plane Anvil Singulation Sawn Singulation (Ref ...

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