IDT71P73804 Integrated Device Technology, IDT71P73804 Datasheet

IDT71P73804

Manufacturer Part Number

IDT71P73804

Description

1.8v 1m X 18 Ddr Ii Pipelined Sram

Manufacturer

Integrated Device Technology

Datasheet

1.IDT71P73804.pdf (25 pages)

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Company:

BOSTOCK HK LIMITED

Part Number:

IDT71P73804S167BQ

Manufacturer:

IDT, Integrated Device Technology Inc

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BOSTOCK HK LIMITED

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IDT71P73804S167BQ8

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IDT, Integrated Device Technology Inc

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BOSTOCK HK LIMITED

Part Number:

IDT71P73804S200BQ

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IDT, Integrated Device Technology Inc

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10 000

Company:

BOSTOCK HK LIMITED

Part Number:

IDT71P73804S200BQ8

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IDT, Integrated Device Technology Inc

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10 000

Company:

BOSTOCK HK LIMITED

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IDT71P73804S250BQ

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IDT, Integrated Device Technology Inc

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Features

Functional Block Diagram

Notes

1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36

2) Represents 19 address signal lines for x8 and x9, 20 address signal lines for x18, and 19 address signal lines for x36.

3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2

4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.

signal lines.

◆

18Mb Density (2Mx8, 2Mx9, 1Mx18, 512Kx36)

Common Read and Write Data Port

Dual Echo Clock Output

4-Word Burst on all SRAM accesses

Multiplexed Address Bus

DDR (Double Data Rate) Data Bus

Depth expansion through Control Logic

HSTL (1.5V) inputs that can be scaled to receive signals

from 1.4V to 1.9V.

Scalable output drivers

1.8V Core Voltage (V

165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

JTAG Interface

Four word bursts data per two clock cycles

One Read or One Write request per two clock

cycles.

Can drive HSTL, 1.8V TTL or any voltage level

from 1.4V to 1.9V.

Output Impedance adjustable from 35 ohms to 70

ohms

DATA

REG

BWx

)

(Note2)

(Note3)

LOGIC

CTRL

GEN

ADD

REG

CLK

(Note2)

18Mb Pipelined

DDR™II SRAM

Burst of 4

SELECT OUTPUT CONTROL

WRITE DRIVER

MEMORY

ARRAY

18M

(Note1)

Description

nous memories with a double-data-rate (DDR), bidirectional data port.

This scheme allows maximization on the bandwidth on the data bus by

passing two data items per clock cycle. The address bus operates at

less than single data rate speeds,allowing the user to fan out addresses

and ease system design while maintaining maximum performance on

data transfers.

and echo clocks, allowing the user to tune the bus for low noise and high

performance.

beyond SRAM devices that use any form of TTL interface. The inter-

face can be scaled to higher voltages (up to 1.9V) to interface with 1.8V

systems if necessary. The device has a V

allowing the user to designate the interface operational voltage, inde-

pendent of the device core voltage of 1.8V V

control allows the user to adjust the drive strength to adapt to a wide

range of loads and transmission lines.

The IDT DDRII

The DDRII has scalable output impedance on its data output bus

All interfaces of the DDRII SRAM are HSTL, allowing speeds

(Note4)

Burst of four SRAMs are high-speed synchro-

6431 drw 16

(Note1)

IDT71P73204

IDT71P73104

IDT71P73804

IDT71P73604

DD.

DDQ

The output impedance

and a separate Vref,

JULY 2005

DSC-6431/00

Related parts for IDT71P73804

IDT71P73804 Summary of contents

Page 1

... WRITE DRIVER ADD (Note2) REG (Note4) 18M MEMORY CTRL ARRAY LOGIC CLK GEN SELECT OUTPUT CONTROL 1 IDT71P73204 IDT71P73104 IDT71P73804 IDT71P73604 TM Burst of four SRAMs are high-speed synchro- and a separate Vref, DDQ The output impedance DD. (Note4) (Note1 6431 drw 16 JULY 2005 DSC-6431/00 ...

Page 2

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Clocking The DDRII SRAM has two sets of input clocks, namely the K, K clocks and ...

Page 3

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Pin Definitions Symbol Pin Function Data I/O signals. Data inputs are sampled on the rising edge ...

Page 4

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Pin Definitions continued Symbol Pin Function DLL Turn Off. When low this input will turn off ...

Page 5

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Pin Configuration IDT71P73204 ( SS ( ...

Page 6

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Pin Configuration IDT71P73104 ( SS ( ...

Page 7

... IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Pin Configuration IDT71P73804 ( Doff V V REF J NC ...

Page 8

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Pin Configuration IDT71P73604 (512K ...

Page 9

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Write Descriptions (1, Signal Write Byte ...

Page 10

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Application Example R Data Bus Address LD R/W BWx/NWx MEMORY ...

Page 11

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Absolute Maximum Ratings Symbol Rating Supply Voltage on V with DD V TERM Respect to GND ...

Page 12

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Parameter Symbol Input Leakage Current ...

Page 13

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Input Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Parameter Symbol Min Input High ...

Page 14

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst Test Conditions Parameter Symbol Core Power Supply Voltage V DD Output Power Supply Voltage V ...

Page 15

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst Electrical Characteristics Symbol Parameter Clock Parameters tKHKH Average clock cycle time (K,K,C,C) tKC var Cycle ...

Page 16

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Timing Waveform of Combined Read and Write Cycles NOP Read A0 Read A1 (burst of 4) ...

Page 17

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 IEEE 1149.1 Test Access Port and Boundary Scan-JTAG This part contains an IEEE standard 1149.1 Compatible ...

Page 18

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Scan Register Definition Part Instrustion Register 512Kx36 3 bits 1Mx18 3 bits 2Mx8/x9 3 bits Identification ...

Page 19

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Boundary Scan Exit Order (2M x 8-Bit, 2Mx9-Bit, 1Mx18-Bit) ORDER PIN ...

Page 20

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Boundary Scan Exit Order (512K x 36-Bit) ORDER PIN ...

Page 21

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 JTAG DC Operating Conditions Parameter Symbol Output Power Supply V DDQ Power Supply Voltage V DD ...

Page 22

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 JTAG AC Characteristics Parameter Symbol TCK Cycle Time t CHCH TCK High Pulse Width t CHCL ...

Page 23

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 (1M x 18-Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Package Diagram Outline for 165-Ball Fine Pitch Grid Array Commercial Temperature Range 6.42 23 ...

Page 24

... XX BQ 165 Fine Pitch Ball Grid Array (fBGA) 250 Clock Frequency in MegaHertz 200 167 IDT71P73204 IDT71P73104 IDT71P73804 DDR II SRAM Burst of 4 IDT71P73604 512K x 36 DDR II SRAM Burst of 4 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com 6.42 24 Commercial Temperature Range ...

Page 25

IDT71P73204 (2M x 8-Bit), 71P73104 (2M x 9-Bit), 71P73804 ( -Bit) 71P73604 (512K x 36-Bit DDR II SRAM Burst of 4 Revision History REV DATE PAGES 0 07/29/05 p. 1-24 DESCRIPTION Released Final datasheet Commercial ...

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