IDT72605 Integrated Device Technology, Inc., IDT72605 Datasheet

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... For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. CMOS SyncBiFIFO 256 and 512 DESCRIPTION: The IDT72605 and IDT72615 are very high-speed, low- power bidirectional First-In, First-Out (FIFO) memories, with synchronous interface for fast read and write cycle times. The SyncBiFIFO information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 PIN CONFIGURATIONS CLK BYP 06 GND PAE PAF A16 D A17 CLK A R PAE AB PAF B17 D B16 GND D D GND B10 G68 Pin 1 Designator BA A0 GND D D GND A10 A11 PGA Top View J68 PLCC Top View 5 ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 PIN CONFIGURATIONS PIN GND 9 10 VCC PN64 TQFP Top View 5.18 COMMERCIAL TEMPERATURE RANGE GND GND 2704 drw 04 3 ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 PIN DESCRIPTION Symbol Name I Data A I/O A0 A17 CS Chip Select Read/Write CLK Clock Enable Output Enable Addresses Data B I/O B0 B17 W R/ Read/Write CLK Clock Enable Output Enable Empty Flag O AB PAE Programmable Almost-Empty Flag PAF Programmable ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 PIN DESCRIPTION (Continued) Symbol Name I Full Flag O BA BYP Port B Bypass O B Flag RS Reset I V Power CC GND Ground ABSOLUTE MAXIMUM RATINGS Symbol Rating Com’l. V Terminal Voltage –0.5 to +7.0 TERM with Respect to Ground T Operating 0 to +70 ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 TEST CONDITIONS In Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load AC ELECTRICAL CHARACTERISTICS (Commercial 10 + Symbol Parameter f Clock frequency CLK t Clock cycle time CLK t Clock HIGH time CLKH t Clock LOW time ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 FUNCTIONAL DESCRIPTION IDTs SyncBiFIFO is versatile for both multiprocessor and peripheral applications. Data can be stored or retrieved from two sources simultaneously. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 NOTES: 1. When 000, the next B A FIFO value is read out of the output register and the read pointer advances selected and bypass data from the Port B input register is read from the Port A output register and its offset is read out through Port A output register. ...

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... PAF Register PAE Register PAF Register NOTE: 1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO. Number of Words in FIFO From LOW 1 n HIGH n+1 D-(m+1) HIGH D-m D-1 HIGH D D HIGH NOTES: PAE n = Programmable Empty Offset ( Register or AB PAF ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 input register and the FIFO memory LOW, data comes out of bus and is read from output register into three-state buffer. In bypass mode bypass messages are transferred into B A output register HIGH, bypass messages are transferred into output register ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 AB, PAE AB, EF BA, PAE BA EF AB, PAE AB, EF BA, PAE CLKH CLK R A17 t SKEW1 READ CLK RSF t RSF t RSS Figure 3. Reset Timing t CLK t CLKL DATA IN VALID NO READ OPERATION Figure 4. Port Write Timing 5.18 COMMERCIAL TEMPERATURE RANGE t RSR NO OPERATION ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 CLK R A17 OE A CLK B t CLKH CLK B R B17 t SKEW1 CLK READ A t CLK t t CLKH CLKL VALID DATA t OLZ WRITE Figure 5. Port Read Timing t CLK t CLKL DATA IN VALID NO READ OPERATION Figure 6. Port Write Timing 5 ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 CLK B R B17 OE B CLK A t CLK t t CLKH CLKL VALID DATA t OLZ WRITE OPERATION Figure 7. Port Read Timing 5.18 COMMERCIAL TEMPERATURE RANGE NO OPERATION OHZ t SKEW1 WRITE 2704 drw 11 13 ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 CLK R A17 0 t SKEW1 CLK B R B17 OE B NOTE: 1. When t minimum specification, t SKEW1 FRL(Max.) t < minimum specification, t SKEW1 FRL(Max.) The Latency Timing applies only at the Empty Boundary ( Figure First Data Word Latency after Reset for Simultaneous Read and Write ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 CLK B R B17 D t SKEW1 CLK R A17 OE A NOTE: 1. When t minimum specification, t SKEW1 FRL(Max.) t < minimum specification, t SKEW1 FRL(Max.) The Latency Timing apply only at the Empty Boundary ( Figure First Data Word Latency after Reset for Simultaneous Read and Write ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 CLK R DATA INPUT A0 A17 t SKEW1 CLK B R FIFO FLAG EF AB BYP B17 OE B NOTES When is brought HIGH Bypass mode will switch to FIFO mode on the following CLK A 2. After the bypass operation is completed, the the next bypass operation. ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 CLK B R BYP B17 t SKEW1 CLK R FIFO FLAG A17 OE A NOTES When is brought HIGH Bypass mode will switch to FIFO mode on the following CLK A 2. After the bypass operation is completed, the the next bypass operation. 3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO mode ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 CLKH CLKL CLK (R WRITE n words in FIFO PAE AB SKEW2 (1) t CLK (R NOTES the minimum time between a rising CLK SKEW2 rising edge of CLK and the rising edge of CLK read is performed on this rising edge of the read clock, there will be Empty + ( words in the FIFO when ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 CLKH CLKL CLK (R WRITE n words in FIFO PAE BA SKEW2 (1) t CLK (R NOTES the minimum time between a rising CLK SKEW2 rising edge of CLK and the rising edge of CLK read is performed on this rising edge of the read clock, there will be Empty + ( words in the FIFO when ...

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... IDT72605/IDT72615 CMOS SyncBiFIFO 256 and 512 ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed X X Package Process/ Temperature Range BLANK Low Power 72605 256 x 18 Parallel Synchronous Bidirectional FIFO 72615 512 x 18 Parallel Synchronous Bidirectional FIFO 5.18 COMMERCIAL TEMPERATURE RANGE ...