LTC1609 LINER [Linear Technology], LTC1609 Datasheet
LTC1609
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LTC1609 Summary of contents
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... LTC1609 R TAG SERIAL INTERFACE DATA 16 DATACLK 15 SYNC 1609 TA01 LTC1609 U 1609 is a 200ksps, serial sampling 16-bit A/D 5V Nonaveraged 4096 Point FFT Plot 0 f SAMPLE f IN –20 SINAD = 87.2dB THD = –100.1dB –40 –60 –80 –100 –120 –130 0 25 ...
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... Digital Input Voltage (Note 4) ........ DGND – 0.3V to 10V Digital Output Voltage ........ DGND – 0. Power Dissipation .............................................. 500mW Operating Ambient Temperature Range LTC1609AC/LTC1609C ............................ LTC1609AI/LTC1609I ......................... – Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 C ANA W U ...
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... LTC1609/LTC1609A MIN TYP MAX 5.25V, 10 5V, etc. (See Tables 1a and 1b) 10 See Tables 1a and 1b LTC1609 LTC1609A TYP MAX MIN TYP MAX 87 – 100 – 100 –96 – 94 – 94 – 102 – 102 – 94 – 94 ...
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... A CONDITIONS (Note 11 25pF L (Note 9) (Note 9) (Notes 10, 17) indicates specifications which apply over the full LTC1609/LTC1609A MIN TYP MAX 2.4 0 –10 A 4.5 = – 200 A 4.0 = 160 A 0.05 = 1.6mA 0.10 0.4 –10 10 LTC1609/LTC1609A MIN TYP MAX 40 100 5 2 260 150 2 UNITS ...
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... Note 17: When data is shifted out during a conversion, with an external data clock, complete the process within 1.2 s from the start of the conversion (BUSY falling). This will help keep any external disturbances from causing an error in the conversion result. LTC1609 LTC1609/LTC1609A MIN TYP MAX UNITS 4 ...
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... LTC1609 W U TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 15 200kHz SAMPLE 14.5 14.0 13.5 13.0 12.5 12.0 11.5 11.0 4.5 5.0 5.5 4.75 5.25 SUPPLY VOLTAGE (V) 1609 G01 Typical INL Curve 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 32768 65535 16384 49152 CODE 1609 G04 SINAD vs Input Frequency FREQUENCY (kHz) 6 Change in CAP Voltage vs Load Current 0 ...
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... CS is low and R/C is high, the level in the TAG pin will be outputted. This can be used to daisy-chain the serial data output from several LTC1609s. If EXT/INT is low, the output data is valid on both the rising and falling edge of the internal shift clock which is outputted on DATACLK. In between conversions, DATA will stay at the level of the TAG input when the conversion was started ...
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... CLOCK U U APPLICATIO S I FOR ATIO Conversion Details The LTC1609 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 16-bit serial output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs ...
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... FS – 1.5LSB and vary the gain trimming resistor until the output code is changing between 1111 1111 1111 1110 and 1111 1111 1111 1111. In the unipolar case, the data is in straight binary format (SB/BTC = HIGH). Figures 4a and 4b show the transfer characteristics of the LTC1609. LinearView is a trademark of Linear Technology Corporation. LTC1609 , R2 ...
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... AGND V AGND IN WITH TRIM LTC1609 R1 IN 200 AGND1 100 33. 50k IN + TRIM 2.2 F CAP 5V 576k GAIN REF 50k + TRIM 2.2 F AGND2 LTC1609 R1 IN 200 AGND1 100 5V 33. 50k V R3 TRIM IN IN CAP 5V + 576k GAIN 2.2 F 50k REF + TRIM 2.2 F AGND2 LTC1609 200 ...
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... OFFSET FIRST AT 0V, THEN ADJUST GAIN) LTC1609 200 AGND1 R2 IN 100 33.2k 2.2 F CAP 5V 5V 576k GAIN 50k REF 50k + TRIM 2.2 F AGND2 LTC1609 R1 IN 200 AGND1 33.2k 100 OFFSET + R3 50k IN TRIM 2.2 F CAP 5V 576k GAIN REF 50k + TRIM 2.2 F AGND2 ...
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... LTC1609 U U APPLICATIO S I FOR ATIO Table 1c. LTC1609 Output Codes for Ideal Input Voltages DESCRIPTION Full-Scale Range 10V 5V Least Significant Bit 305 V 153 V +Full Scale (FS – 1LSB) 9.999695V 4.999847V 3.339898V Midscale 0V 0V 1LSB Below Midscale – 305 V –153 V – Full Scale – ...
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... FFT algorithm, the ADC’s spectral content can be examined for frequencies outside the fundamental. Figure 6 shows a typical LTC1609 FFT plot which yields a SINAD of 87.2dB and THD of – 100dB. Signal-to-Noise Ratio The Signal-to-Noise and Distortion Ratio (SINAD) is the ...
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... EXT/INT pin low puts the part in the internal clock mode and the DATACLK pin becomes a digital output. Internal Clock Mode With the EXT/INT pin tied low, the LTC1609 provides the data clock on the DATACLK pin. The timing diagram is shown in Figure 8. Typically tied low and the R/C pin is used to start a conversion ...
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... APPLICATIO S I FOR ATIO External Clock Mode With the EXT/INT pin tied high, the DATACLK pin becomes a digital input and the LTC1609 can accept an externally supplied data clock. There are several ways in which the conversion results can be clocked out. The data can be clocked out during or after a conversion with a continuous or discontinuous data clock ...
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... LTC1609 U U APPLICATIO S I FOR ATIO External Data Clock Data Read After the Conversion Figure 10 shows how the result from the current conver- sion can be read out after the conversion has been com- pleted. The externally supplied data clock is running continuously. CS and R/C are first used together to initiate a conversion and then CS is used to read the result ...
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... Figure 13 shows how this feature can be used. R/C, CS and the DATACLK are tied together on both LTC1609s. CS can be grounded if a discontinuous data clock is used. A falling edge on R/C will allow both LTC1609s to capture their respective analog input signals simultaneously ...
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... R/C device #1’s TAG input. A minimum of 34 clock pulses are DCLK needed to shift out the results from both LTC1609s assuming the data is captured on the falling clock edge. Using the highest frequency permitted for DATACLK 1609 F13 (20MHz), a 200kHz throughput can still be achieved ...
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... DATA B15 B14 B13 B12 B11 B10 OUT Figure 14. Data Output from Cascading Two (CS = Low, TAG (#2) = Low) LTC1609s Together Output Data Format The SB/BTC pin controls the format of the serial digital output word. With the pin tied high the format is straight binary. With the pin tied low the data format is two’ ...
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... LTC1609 U U APPLICATIO S I FOR ATIO R4 200 E15 R4 R5 100 E16 33k E17 R6 5V JP1 Figure 15a. LTC1609 “Postage Stamp” Evaluation Circuit Schematic DIG 2 27 AGND1 V ANA PWRD BUSY ...
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... APPLICATIO S I FOR ATIO Figure 15b. LTC1609 “Postage Stamp” Evaluation Board Silkscreen (2 Actual Size) Figure 15d. LTC1609 “Postage Stamp” Evaluation Board Bottom Metal Layer (2 Actual Size Figure 15c. LTC1609 “Postage Stamp” Evaluation Board Top Metal Layer (2 Actual Size) LTC1609 1609fa 21 ...
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... OUT LTC1609 200 AGND1 R2 100 33.2k R3 OFFSET LTC1662 + TRIM 2 OUTA CAP GND GAIN V CC 787k TRIM REF V OUTB + 2.2 F AGND2 0.1 F LTC1609 R1 200 AGND1 33.2k 100 OFFSET + R3 LTC1662 TRIM 2 OUTA CAP GND GAIN V CC 787k TRIM V REF OUTB + 2.2 F AGND2 0.1 F LTC1609 200 ...
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... LTC DWG # 05-08-1640 – 8 .65 (.0256) BSC .25 – .38 (.010 – .015) LTC1609 10.07 – 10.33* (.397 – .407 7.65 – 7.90 (.301 – .311 1.73 – 1.99 (.068 – .078) .05 – .21 (.002 – .008) ...
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... LTC1609 PACKAGE DESCRIPTIO 0.291 – 0.299** (7.391 – 7.595) 0.010 – 0.029 45 (0.254 – 0.737) 0.009 – 0.013 NOTE 1 (0.229 – 0.330) 0.016 – 0.050 (0.406 – 1.270) NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. ...