LTC2421 LINER [Linear Technology], LTC2421 Datasheet
LTC2421
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LTC2421 Summary of contents
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... This eliminates the latency found in conventional converters and simplifies multiplexed applications. Through a single pin, the LTC2421/LTC2422 can be configured for better than 110dB rejection at 50Hz or 60Hz 2%, or can be driven by an external oscillator for a user defined rejection frequency in the range 1Hz to 120Hz ...
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... Power Supply Rejection, 60Hz 2% FS SET Power Supply Rejection, 50Hz 2% FS SET 2 U RATINGS (Notes 1, 2) Operating Temperature Range + 0.3V) LTC2421/LTC2422C ................................ LTC2421/LTC2422I ............................ – 0.3V 0.3V) Storage Temperature Range ................. – 150 C CC Lead Temperature (Soldering, 10 sec).................. 300 C + 0.3V LTC2421CMS V 1 ...
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... 1.6mA – 800 A (Note 10 1.6mA (Note 10) O The denotes specifications which apply over the full operating temperature range, CONDITIONS (Note 12 (Note 12) CC LTC2421/LTC2422 MIN TYP MAX UNITS ZS – 0.12V FS + 0.12V SET REF SET REF 0 SET CC ...
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... LTC2421/LTC2422 CHARACTERISTICS range, otherwise specifications are at T SYMBOL PARAMETER f External Oscillator Frequency Range EOSC t External Oscillator High Period HEO t External Oscillator Low Period LEO t Conversion Time CONV f Internal SCK Frequency ISCK D Internal SCK Duty Cycle ISCK f External SCK Frequency Range ...
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... T = – –6 – – –10 5.00 5.05 5.10 5.15 5.20 5.25 5.30 INPUT VOLTAGE (V) 24212 G08 LTC2421/LTC2422 Negative Extended Input Range Total Unadjusted Error (3V Supply 2.5V REF – –55 C –2 A – ...
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... LTC2421/LTC2422 W U TYPICAL PERFOR A CE CHARACTERISTICS RMS Noise vs Reference Voltage REFERENCE VOLTAGE (V) 24212 G10 Noise Histogram 350 REF 300 250 200 150 100 50 0 – OUTPUT CODE (ppm) ...
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... REF – 2. –40 –60 –80 –100 SAMPLE RATE = 15.36kHz 2% –120 15100 15200 15300 15400 12 FREQUENCY AT V (Hz) IN LTC2421/LTC2422 Rejection vs Frequency 4. – –40 –60 –80 –100 –120 1 100 95 120 FREQUENCY AT V 24212 G20 ...
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... REF absolute maximum rating of – 0. sions are performed alternately between CH0 and CH1 for the LTC2422. Pin Connect (NC) on the LTC2421. ZS (Pin 5): Zero-Scale Set Input. This pin defines the SET zero-scale input value. When V ...
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... W ADC = 20pF LOAD 24212 TC01 LTC2421/LTC2422 pin is connected pin is connected O = 0V), the converter uses its internal oscillator ...
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... CS SCK SDO EOC = 1 CONVERSION Figure 1. LTC2421/LTC2422 Compatible Timing with the LTC2401/LTC2402 Once CS is pulled LOW and SCK rising edge is applied, the device begins outputting the conversion result. There is no latency in the conversion result. The data output corre- sponds to the conversion just performed ...
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... W U above. The first conversion result following POR is accu- rate within the specifications of the device. Reference Voltage Range The LTC2421/LTC2422 can accept a reference voltage ( – ZS SET noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly con- stant with reference voltage. A decrease in reference volt- age will not significantly improve the converter’ ...
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... REF temperature dependency. Output Data Format The LTC2421/LTC2422 serial output data stream is 24 bits long. The first 4 bits represent status information indicat- ing the sign, selected channel, input range and conversion state. The next 20 bits are the conversion result, MSB first. ...
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... REF V < –1/8 • CH0/CH1 IN REF *Bit 22 is always 0 for the LTC2421 **The sign bit changes state during the 0 code. As long as the voltage on the V pin is maintained within IN the – 0. 0.3V) absolute maximum operating CC range, a conversion result is generated for any input value from – ...
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... SDO pin on the falling edge of the serial clock. In the Internal SCK mode of operation, the SCK pin output and the LTC2421/LTC2422 create their own serial 24212 F05 clock by dividing the internal conversion clock the External SCK mode of operation, the SCK pin is used as input ...
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... In addition, the CS signal can be used to trigger a new conversion cycle before the entire serial data transfer has been completed. The LTC2421/LTC2422 will abort any serial data transfer in progress and start a new conversion cycle anytime a LOW-to-HIGH transition is detected at the CS pin after the converter has entered the data output state (i ...
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... LTC2421/LTC2422 U U APPLICATIO S I FOR ATIO At the conclusion of the data cycle, CS may remain LOW and EOC monitored as an end-of-conversion interrupt. Alternatively, CS may be driven HIGH setting SDO to Hi-Z. As described above, CS may be pulled LOW at any time in order to monitor the conversion status. Typically, CS remains LOW during the data output state. ...
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... SET SET BIT 23 BIT 22 BIT 21 BIT 20 BIT 19 EOC CH0/CH1 SIG EXR MSB DATA OUTPUT Figure 8. External Serial Clock Operation LTC2421/LTC2422 INTERNAL OSC/50Hz REJECTION = EXTERNAL CLOCK SOURCE = INTERNAL OSC/60Hz REJECTION 2-WIRE SERIAL I/O BIT 18 BIT 4 BIT 0 LSB 20 CONVERSION 24212 F08 24212f ...
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... SCK pin or by never pulling CS HIGH when SCK is LOW. , the first rising Whenever SCK is LOW, the LTC2421/LTC2422’s internal pull-up at pin SCK is disabled. Normally, SCK is not exter- nally driven if the device is in the internal SCK timing mode. ...
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... SCK and the last bit of the conversion result can be latched on the 24th rising edge of SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1) indicating a new conversion is in progress. SCK remains HIGH during the conversion. LTC2421/LTC2422 ...
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... SCK is floating important to ensure there are no external drivers pulling SCK LOW while CS is discharging. DIGITAL SIGNAL LEVELS The LTC2421/LTC2422’s digital interface is easy to use. Its digital inputs (F operation) accept standard TTL/CMOS logic levels and the internal hysteresis receivers can tolerate edge rates as slow as 100 s ...
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... CAPACITANCE ON CS (pF) Figure 14. CS Capacitance vs Output Rate In order to preserve the LTC2421/LTC2422’s accuracy very important to minimize the ground path impedance which may appear in series with the input and/or reference signal and to reduce the current which may flow through this path. The GND pin should be connected to a low ...
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... Parallel termination near the LTC2421/LTC2422 pin will eliminate this problem but will increase the driver power dissipation. A series resistor between 27 and 56 placed near the driver or near the LTC2421/LTC2422 pin will also eliminate this problem without additional power dissipa- tion. The actual resistor value depends upon the trace impedance and connection topology ...
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... FS SET 24212 F17 V IN LTC2421/ PAR LTC2422 20pF 24212 F17 IN 10k 100k 24212 F19 Figure 21. Full-Scale Error vs R (Small C) LTC2421/LTC2422 (see Figure 18) is small IN < 0. function IN > 0.01 F), the input and when REF 35 C ...
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... LTC2421/LTC2422 U U APPLICATIO S I FOR ATIO 10 0 – 0pF 100pF – 1000pF IN – 0. –40 REF – 100 SOURCE Figure 22. Full-Scale Error addition to the input current spikes, the input ESD pro- tection diodes have a temperature dependent leakage cur- rent ...
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... As a result of the oversampling ratio (256) and the digital filter, minimal (if any) antialias filtering is required in front of the LTC2421/LTC2422. If passive RC components are placed in front of the LTC2421/LTC2422, the input dy- namic current should be considered (see Input Current section). In cases where large effective RC time constants are used, an external buffer amplifier may be required to minimize the effects of input dynamic current ...
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... R flows through parasitic resistors R Figure 29. The voltage drop across these parasitic resis- tors leads to systematic offset and full-scale errors. In order to eliminate the errors associated with these para- sitic resistors, the LTC2421/LTC2422 include a full-scale set input (FS ( shown in Figure 30, the FS SET zero current full-scale sense input. Errors due to parasitic " ...
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... ZS SET SET dynamic input range (– 300mV to 5.3V) and low noise (1.2ppm RMS) enable the LTC2421 or the LTC2422 to directly digitize the output of the bridge sensor. The LTC2422 is ideal for applications requiring continu- ous monitoring of two input sensors. As shown in Figure 32, the LTC2422 can monitor both a thermocouple temperature probe and a cold junction temperature sen- sor ...
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... LTC2421/LTC2422 U U APPLICATIO S I FOR ATIO The selection between CH0 and CH1 is automatic. Initially, after power-up, a conversion is performed on CH0. For each subsequent conversion, the input channel selection is alternated. Embedded within the serial data output is a status bit indicating which channel corresponds to the conversion result ...
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... A EXCITATION CH0 R1 1000pF I = 200 A EXCITATION 3 CH1 SET R2 0.1 F Figure 35. RTD Remote Temperature Measurement LTC2421/LTC2422 + R1 • I The result of the RTD EXCITATION. EXCITATION. + 300mV. Adding the two conversion REF . RTD SCK 8 3-WIRE SDO SPI INTERFACE ...
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... LTC2421/LTC2422 U U APPLICATIO S I FOR ATIO Below 4.2V, the LTC1535’s driver outputs Y and Z are in a high impedance state, allowing the 1k pull-down to de- fine the logic state at SCK. When the LTC2422 first be- comes active, it samples SCK; a logic “0” provided by the 1k pull-down invokes the external serial clock mode. In ...
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... BSC 4.88 0.10 DETAIL “A” (.192 .004) 0 – 6 TYP 0.53 0.01 (.021 .006) 1.10 (.043) DETAIL “A” MAX SEATING PLANE 0.17 – 0.27 (.007 – .011) LTC2421/LTC2422 0.497 0.076 (.0196 .003 REF 3.00 0.102 (.118 .004) NOTE 0.86 (.034) REF 0.13 0.05 (.005 .002) ...
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... Isolation RMS 4ppm INL, 10ppm Total Unadjusted Error, 200 A ADC in MSOP 0.6ppm Noise, 4ppm INL, Pin Compatible with the LTC2421/LTC2422 ADC 4ppm INL, 10ppm Total Unadjusted Error, 200 A Simultaneous 50Hz and 60Hz Rejection, 0.16ppm Noise ADC 15Hz Output Rate at 60Hz Rejection, Pin Conpatible with the LTC2410 1 ...