LTC2619 Linear Technology Corporation, LTC2619 Datasheet
LTC2619
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LTC2619 Summary of contents
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... DACs and advance performance standards for output drive and load regulation in single-supply, voltage-output DACs. The parts use a 2-wire, I LTC2609/LTC2619/LTC2629 operate in both the standard mode (clock rate of 100kHz) and the fast mode (clock rate of 400kHz). The LTC2609/LTC2619/LTC2629 incorporate a power-on reset circuit. During power-up, the voltage outputs rise less than 10mV above zero scale ...
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... OS Coefficient GE Gain Error Gain Temperature Coefficient (Note 1) Operating Temperature Range: LTC2609C/LTC2619C/LTC2629C LTC2609C-1/LTC2619C-1/LTC2629C-1 ... 0°C to 70°C LTC2609I/LTC2619I/LTC2629I LTC2609I-1/LTC2619I-1/LTC2629I-1 .. – 40°C to 85° ORDER PART NUMBER LTC2609CGN LTC2609CGN-1 15 REFD LTC2609IGN 14 V LTC2609IGN-1 OUTD 13 V LTC2619CGN ...
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... IN C Capacitive Load for Each Bus Line B C External Capacitive Load on Address CAX Pins LTC2609/LTC2619/LTC2629 ● The denotes specifications which apply over the full operating = 25°C. REFA = REFB = REFC = REFD = 4.096V (V A unloaded, unless otherwise noted. (Note 9) OUT CONDITIONS ± ...
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... REF and 3/4 scale to 1/4 scale. Load parallel with 200pF to GND. 4 ● The denotes specifications which apply over the full operating = 25°C. REFA = REFB = REFC = REFD = 4.096V (V A unloaded, unless otherwise noted. OUT LTC2629/LTC2629-1 LTC2619/LTC2619-1 LTC2609/LTC2609-1 MIN TYP MAX 7 2.7 0.7 1000 12 180 120 ...
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... Settling to ±1LSB V OUT 100µV/DIV 9TH CLOCK OF 3RD DATA SCL BYTE 2V/DIV 2µs/DIV 4.096V CC REF 1/4 SCALE TO 3/4 SCALE STEP 200pF L L AVERAGE OF 2048 EVENTS LTC2609/LTC2619/LTC2629 Differential Nonlinearity (DNL 4.096V REF 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 16384 32768 ...
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... LTC2609/LTC2619/LTC2629 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2619 Integral Nonlinearity (INL 4.096V REF –2 –4 –6 –8 0 4096 8192 12288 16383 CODE 2609 G09 LTC2629 Integral Nonlinearity (INL) 2 4.096V REF 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 1024 2048 ...
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... TEMPERATURE (°C) 2609 G18 Gain Error 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 2 LTC2609/LTC2619/LTC2629 Load Regulation 1.0 CODE = MIDSCALE 0.8 0.6 0.4 0 REF CC –0.2 –0 REF CC –0.6 –0.8 –1.0 –35 –25 –15 – (mA) ...
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... LTC2609/LTC2619/LTC2629 W U TYPICAL PERFOR A CE CHARACTERISTICS LTC2609/LTC2619/LTC2629 Large-Signal Response V OUT 0.5V/DIV REF CC 1/4 SCALE TO 3/4 SCALE 2.5µs/DIV 2609 G23 Headroom at Rails vs Output Current 5.0 5V SOURCING 4.5 4.0 3.5 3V SOURCING 3.0 2.5 2.0 1.5 1.0 5V SINKING 0.5 3V SINKING (mA) OUT 2609 G26 8 Midscale Glitch Impulse TRANSITION FROM ...
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... OUT 5. 5.6V REF CODE = SWEPT OUT 1V/DIV LTC2609/LTC2619/LTC2629 Output Voltage Noise, 0.1Hz to 10Hz V OUT 10µV/DIV 0 100k 1M 2609 G29 Short-Circuit Output Current vs V OUT REF CODE = FULL SCALE –10 V OUT –20 –30 – ...
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... LTC2609/LTC2619/LTC2629 PIN FUNCTIONS GND (Pin 1): Analog Ground. REFLO (Pin 2): Reference Low. The voltage at this pin sets the zero scale (ZS) voltage of all DACs. This pin can be raised above ground ground 3V. CC REFA to REFD (Pins 3, 6, 12, 15): Reference Voltage Inputs for each DAC. REFx sets the full-scale voltage of the DACs. REFLO ≤ ...
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... W BLOCK DIAGRA REFA 3 DAC OUTA V OUTB DAC B 5 REFB 6 SCL 8 SDA 9 LTC2609/LTC2619/LTC2629 V REFLO GND CONTROL LOGIC 32-BIT SHIFT REGISTER ADDRESS DECODE INTERFACE 15 REFD DAC OUTD DAC OUTC 12 REFC 11 CA0 10 CA1 LOGIC 7 CA2 2609 BD 26091929f 11 ...
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... LTC2609/LTC2619/LTC2629 TEST CIRCUITS Test Circuit 1 100Ω IH( IL( DIAGRA S SDA LOW r SCL t HD(STA HD(DAT) ALL VOLTAGE LEVELS REFER SU(DAT HD(STA) t SU(STA HIGH AND V LEVELS IH(MIN) IL(MAX) Figure 1 Test Circuit 2 ...
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... I C bus operating in the fast mode, an active pull-up will be necessary if the bus capacitance is greater than 200pF. The LTC2609/LTC2619/LTC2629 are receive-only (slave) devices. The master can write to the LTC2609/LTC2619/ LTC2629. The LTC2609/LTC2619/LTC2629 do not re- spond to a read from the master. + 0.3V (see Absolute The START (S) and STOP (P) Conditions When the bus is not in use, both SCL and SDA must be high ...
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... The 16-bit data word consists of the 16-, 14- or 12-bit input code, MSB to LSB, followed don’t care bits (LTC2609, LTC2619 and LTC2629 respectively). A typical LTC2609 write transaction is shown Figure 4 ...
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... U OPERATIO Write Word Protocol for LTC2609/LTC2619/LTC1629 S SLAVE ADDRESS Input Word (LTC2609 1ST DATA BYTE Input Word (LTC2619 1ST DATA BYTE Input Word (LTC2629 1ST DATA BYTE Table 2 COMMAND Write to Input Register n ...
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... LTC2609/LTC2619/LTC2629 U OPERATIO then the main bias generation circuit block has been automatically shut down in addition to the individual DAC amplifiers and reference inputs. In this case, the power-up delay time is 12µs (for V = 5V) or 30µs (for V CC Voltage Output The rail-to-rail amplifier has guaranteed load regulation when sourcing or sinking up to 15mA ...
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... U OPERATIO LTC2609/LTC2619/LTC2629 26091929f 17 ...
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... LTC2609/LTC2619/LTC2629 U OPERATIO 18 26091929f ...
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... Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. LTC2609/LTC2619/LTC2629 REFA REFB REFC JP3 ...
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... LTC2609/LTC2619/LTC2629 PACKAGE DESCRIPTIO .254 MIN .0165 ± .0015 RECOMMENDED SOLDER PAD LAYOUT .007 – .0098 (0.178 – 0.249) .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE RELATED PARTS PART NUMBER DESCRIPTION LTC1458/LTC1458L ...