MC100LVE210 ON Semiconductor, MC100LVE210 Datasheet

MC100LVE210

Manufacturer Part Number

MC100LVE210

Description

Low Voltage Dual 1:4 / 1:5 Differential Fanout Buffer

Manufacturer

ON Semiconductor

Datasheet

1.MC100LVE210.pdf (8 pages)

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MC100LVE210, MC100E210

Low Voltage Dual 1:4, 1:5

Differential Fanout Buffer

ECL/PECL Compatible

ECL fanout buffer designed with clock distribution in mind. The

device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single

chip. The device features fully differential clock paths to minimize

both device and system skew. The dual buffer allows for the fanout of

two signals through a single chip, thus reducing the skew between the

two fundamental signals from a part–to–part skew down to an

output–to–output skew. This capability reduces the skew by a factor of

4 as compared to using two LVE111’s to accomplish the same task.

The MC100LVE210 works from a –3.3V supply while the

MC100E210 provides identical function and performance from a

standard –4.5V 100E voltage supply.

reference voltage is supplied. For single–ended input applications the

V BB reference should be connected to the unused CLK input of a

differential pair and bypassed to ground via a 0.01 f capacitor. The

input signal is then driven into the selected CLK input.

both sides of the differential output are identically terminated, even if

only one side is being used. In most applications all nine differential

pairs will be used and therefore terminated. In the case where fewer

than nine pairs are used it is necessary to terminate at least the output

pairs adjacent to the output pair being used in order to maintain

minimum skew. Failure to follow this guideline will result in small

degradations of propagation delay (on the order of 10–20ps) of the

outputs being used, while not catastrophic to most designs this will

result in an increase in skew. Note that the package corners isolate

outputs from one another such that the guideline expressed above

holds only for outputs on the same side of the package.

from a positive V CC supply in PECL mode. This allows the LVE210 to

be used for high performance clock distribution in +3.3V systems.

Designers can take advantage of the LVE210’s performance to

distribute low skew clocks across the backplane or the board. In a

PECL environment series or Thevenin line terminations are typically

used as they require no additional power supplies, if parallel

termination is desired a terminating voltage of V CC –2.0V will need to

be provided. For more information on using PECL, designers should

refer to Application Note AN1406/D.

February, 2000 – Rev. 2

The MC100LVE210 is a low voltage, low skew dual differential

For applications which require a single–ended input, the V BB

To ensure that the tight skew specification is met it is necessary that

The MC100LVE210, as with most ECL devices, can be operated

Dual Differential Fanout Buffers

200ps Part–to–Part Skew

50ps Typical Output–to–Output Skew

Low Voltage ECL/PECL Compatible

28–lead PLCC Packaging

Semiconductor Components Industries, LLC, 1999

*For additional information, see Application Note

MC100LVE210FN

MC100LVE210FNR2

MC100E210FN

MC100E210FNR2

AND8002/D

MC100LVE210

MC100E210FN

AWLYYWW

Device

ORDERING INFORMATION

MARKING DIAGRAM*

http://onsemi.com

PLCC PACKAGE

FN SUFFIX

CASE 776

Package

PLCC

WL = Wafer Lot

YY = Year

WW = Work Week

WL = Wafer Lot

YY = Year

WW = Work Week

Publication Order Number:

= Assembly Location

MC100LVE210/D

500 Tape & Reel

37 Units / Rail

Shipping

Related parts for MC100LVE210

MC100LVE210 Summary of contents

Page 1

... Low Voltage Dual 1:4, 1:5 Differential Fanout Buffer ECL/PECL Compatible The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer single chip. The device features fully differential clock paths to minimize both device and system skew ...

Page 2

... MC100LVE210, MC100E210 Qa0 Qa0 Qa1 V CCO Qa1 Qa2 CLKa 28 Pinout: 28–Lead PLCC (Top View) CLKa 2 3 CLKb CLKb Qb4 Qb4 Qb3 V CCO Qb3 Qb2 CLKa CLKa CLKb CLKb V BB Qa2 19 18 ...

Page 3

... V CMR is defined as the range within which the V IH level may vary, with the device still meeting the propagation delay specification. The V IL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal (min). MC100LVE210, MC100E210 0 C ...

Page 4

Page 5

... MC100LVE210, MC100E210 Y BRK -N- -L- - 0.007 (0.180 0.007 (0.180 VIEW S G1 0.010 (0.250 – NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. ...

Page 6

... Notes MC100LVE210, MC100E210 http://onsemi.com 6 ...

Page 7

... Notes MC100LVE210, MC100E210 http://onsemi.com 7 ...

Page 8

... English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time) Email: ONlit@hibbertco.com EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781 *Available from Germany, France, Italy, England, Ireland MC100LVE210, MC100E210 CENTRAL/SOUTH AMERICA: Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST) Email: ONlit–spanish@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor – ...

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