MC10EP52 ON Semiconductor, MC10EP52 Datasheet
MC10EP52
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MC10EP52 Summary of contents
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... MC10EP52, MC100EP52 3. ECL Differential Data and Clock D Flip−Flop Description The MC10EP/100EP52 is a differential data, differential clock D flip−flop. The device is pin and functionally equivalent to the EL52 device. Data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock ...
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Flip-Flop CLK 3 CLK 4 Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 3. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack ...
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Table 4. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out I V Sink/Source Operating Temperature ...
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Table 6. 10EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...
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Table 8. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 12 Output LOW Voltage (Note 12 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...
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Table 10. 100EP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 18 Output LOW Voltage (Note 18 Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...
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V 0.8 3.3 V 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 FREQUENCY (MHz) Figure Driver Device Figure 3. Typical ...
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... ORDERING INFORMATION Device MC10EP52D MC10EP52DG MC10EP52DR2 MC10EP52DR2G MC10EP52DT MC10EP52DTG MC10EP52DTR2 MC10EP52DTR2G MC10EP52MNR4 MC10EP52MNR4G MC100EP52D MC100EP52DG MC100EP52DR2 MC100EP52DR2G MC100EP52DT MC100EP52DTG MC100EP52DTR2 MC100EP52DTR2G MC100EP52MNR4 MC100EP52MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D ...
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Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
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... C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004) ...
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K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) −T− D SEATING G PLANE PACKAGE DIMENSIONS TSSOP−8 ...
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... AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A 0.80 1.00 A1 0.00 0.05 A3 0.20 REF b 0.20 0.30 2.00 BSC D D2 1.10 1.30 E 2.00 BSC E2 0.70 0.90 e 0.50 BSC K 0.20 −−− L 0.25 0.35 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC10EP52/D ...