MC9S08QG8CDTE Freescale Semiconductor, MC9S08QG8CDTE Datasheet

IC MCU 8K FLASH 10MHZ 16-TSSOP

MC9S08QG8CDTE

Manufacturer Part Number
MC9S08QG8CDTE
Description
IC MCU 8K FLASH 10MHZ 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet

Specifications of MC9S08QG8CDTE

Core Processor
HCS08
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
512Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
16
Package Type
TSSOP
Processor Series
S08QG
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
512 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
1
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08QG8E
Minimum Operating Temperature
- 40 C
Package
16TSSOP
Family Name
HCS08
Maximum Speed
20 MHz
For Use With
DEMO9S08QG8E - BOARD DEMO FOR MC9S08QG8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08QG8CDTE
Manufacturer:
ABB
Quantity:
101
Part Number:
MC9S08QG8CDTE
Manufacturer:
Freescale Semiconductor
Quantity:
41 991
Part Number:
MC9S08QG8CDTE
Manufacturer:
FREESCALE
Quantity:
500
Part Number:
MC9S08QG8CDTE
Manufacturer:
FREESCALE
Quantity:
500
Part Number:
MC9S08QG8CDTE
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MC9S08QG8CDTER
0
MC9S08QG8
MC9S08QG4
Data Sheet
HCS08
Microcontrollers
MC9S08QG8
Rev. 5
11/2009
freescale.com

Related parts for MC9S08QG8CDTE

MC9S08QG8CDTE Summary of contents

Page 1

MC9S08QG8 MC9S08QG4 Data Sheet HCS08 Microcontrollers MC9S08QG8 Rev. 5 11/2009 freescale.com ...

Page 2

...

Page 3

MC9S08QG8/4 Features 8-Bit HCS08 Central Processor Unit (CPU) • 20-MHz HCS08 CPU (central processor unit) • HC08 instruction set with added BGND instruction • Background debugging system • Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two ...

Page 4

...

Page 5

... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2007-2009. All rights reserved. MC9S08QG8 Data Sheet Covers MC9S08QG8 MC9S08QG4 MC9S08QG8 Rev. 5 11/2009 ...

Page 6

... Incorporated core team markups from shared review. See Project Sync issue 4 2/2008 #3313 for archive. Added new part number information for the maskset revision 4. 5 11/2009 Corrected bit 0 of KBISC register in the © Freescale Semiconductor, Inc., 2007-2008. All rights reserved. Description of Changes Table 4-2. ...

Page 7

This product incorporates SuperFlash from SST. ® Technology licensed ...

Page 8

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev PRELIMINARY Freescale Semiconductor ...

Page 9

... Serial Communications Interface (S08SCIV3)..................... 191 Chapter 15 Serial Peripheral Interface (S08SPIV3) ................................ 211 Chapter 16 Timer/Pulse-Width Modulator (S08TPMV2) ......................... 227 Chapter 17 Development Support ........................................................... 243 Appendix A Electrical Characteristics...................................................... 265 Appendix B Ordering Information and Mechanical Drawings................ 289 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor List of Chapters Title Page 7 ...

Page 10

...

Page 11

... MC9S08QG8/4 Memory Map ........................................................................................................ 39 4.2 Reset and Interrupt Vector Assignments ......................................................................................... 40 4.3 Register Addresses and Bit Assignments........................................................................................ 41 4.4 RAM................................................................................................................................................ 45 4.5 FLASH ............................................................................................................................................ 46 4.5.1 Features ..............................................................................................................................47 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 External Signal Description Chapter 3 Modes of Operation Chapter 4 Page ...

Page 12

... System Real-Time Interrupt Status and Control Register (SRTISC).................................73 5.8.8 System Power Management Status and Control 1 Register (SPMSC1) ............................74 5.8.9 System Power Management Status and Control 2 Register (SPMSC2) ............................75 5.8.10 System Power Management Status and Control 3 Register (SPMSC3) ............................76 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Title Chapter 5 Page Freescale Semiconductor ...

Page 13

... BGND Instruction..............................................................................................................95 7.5 HCS08 Instruction Set Summary .................................................................................................... 96 Analog Comparator (S08ACMPV2) 8.1 Introduction ................................................................................................................................... 107 8.1.1 ACMP Configuration Information...................................................................................107 8.1.2 ACMP/TPM Configuration Information .........................................................................107 8.1.3 Features ............................................................................................................................109 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Title Chapter 6 Parallel Input/Output Control Chapter 7 Chapter 8 Page 11 ...

Page 14

... MCU Stop1 and Stop2 Mode Operation..........................................................................135 9.5 Initialization Information .............................................................................................................. 135 9.5.1 ADC Module Initialization Example ..............................................................................135 9.6 Application Information................................................................................................................ 137 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Title Chapter 9 )...................................................................................................121 DDAD )..................................................................................................121 SSAD ) ....................................................................................121 REFH ) .....................................................................................121 REFL Page Freescale Semiconductor ...

Page 15

... IIC Address Register (IICA)............................................................................................159 11.3.2 IIC Frequency Divider Register (IICF) ...........................................................................159 11.3.3 IIC Control Register (IICC) .............................................................................................162 11.3.4 IIC Status Register (IICS)................................................................................................163 11.3.5 IIC Data I/O Register (IICD) ...........................................................................................164 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Title Chapter 10 Chapter 11 Page 13 ...

Page 16

... MTIM Clock Configuration Register (MTIMCLK)........................................................187 13.3.3 MTIM Counter Register (MTIMCNT)............................................................................188 13.3.4 MTIM Modulo Register (MTIMMOD)...........................................................................188 13.4 Functional Description .................................................................................................................. 189 13.4.1 MTIM Operation Example ..............................................................................................190 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Title Chapter 12 Keyboard Interrupt (S08KBIV2) Chapter 13 Modulo Timer (S08MTIMV1) Page Freescale Semiconductor ...

Page 17

... Modes of Operation....................................................................................................................... 217 15.3.1 SPI in Stop Modes ...........................................................................................................217 15.4 Register Definition ........................................................................................................................ 217 15.4.1 SPI Control Register 1 (SPIC1) .......................................................................................217 15.4.2 SPI Control Register 2 (SPIC2) .......................................................................................218 15.4.3 SPI Baud Rate Register (SPIBR).....................................................................................219 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Title Chapter 14 Chapter 15 Page 15 ...

Page 18

... Introduction ................................................................................................................................... 243 17.1.1 Module Configuration......................................................................................................243 17.1.2 Features ............................................................................................................................244 17.2 Background Debug Controller (BDC) .......................................................................................... 244 17.2.1 BKGD Pin Description ....................................................................................................245 17.2.2 Communication Details ...................................................................................................246 17.2.3 BDC Commands ..............................................................................................................248 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Title Chapter 16 Chapter 17 Development Support Page Freescale Semiconductor ...

Page 19

... A.12.1 Radiated Emissions..........................................................................................................286 A.12.2 Conducted Transient Susceptibility .................................................................................286 Ordering Information and Mechanical Drawings B.1 Ordering Information .....................................................................................................................289 B.1.1 Device Numbering Scheme .............................................................................................289 B.2 Mechanical Drawings.....................................................................................................................289 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Title Appendix A Electrical Characteristics Appendix B Page 17 ...

Page 20

... Section Number MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Title Page Freescale Semiconductor ...

Page 21

... TPM 2-ch 12 I/O 1 Output 1 Output only I/O pins only 1 Input only 1 Input only 24 QFN 16 PDIP Package 16 QFN Types 16 TSSOP MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Device MC9S08QG8 16-Pin 8-Pin 8K 512 yes no yes yes 8-ch 4-ch yes yes yes 8-pin ...

Page 22

... Figure 1-1. MC9S08QG8/4 Block Diagram MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 BKGD/MS IRQ TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS SCL PTA3/KBIP3/SCL/ADP3 SDA PTA2/KBIP2/SDA/ADP2 4 4 PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 4 PTB7/SCL/EXTAL 4 PTB6/SDA/XTAL TPMCH0 TPMCH1 SS PTB5/TPMCH1/SS MISO PTB4/MISO MOSI PTB3/KBIP7/MOSI/ADP7 SPSCK PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 Freescale Semiconductor ...

Page 23

... ICSLCLK** 1-kHz ICSERCLK* * ICSERCLK requires XOSC module. ** ICSLCLK is the alternate BDC clock source for the MC9S08QG8/4. Figure 1-2. System Clock Distribution Diagram MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Table 1-2. Versions of On-Chip Modules Module (ACMP) (ADC) (CPU) (IIC) (ICS) ...

Page 24

... Chapter 1 Device Overview MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Freescale Semiconductor ...

Page 25

... Device Pin Assignment The following figures show the pin assignments for the available packages. Refer to package types are available for each device in the series. PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 1 8 PTA0/KBIP0/TPMCH0/ADP0/ACMP PTA1/KBIP1/ADP1/ACMP– ...

Page 26

... V 14 PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTB0/KBIP4/RxD/ADP4 6 11 PTB1/KBIP5/TxD/ADP5 PTB6/SDA/XTAL 7 10 PTB2/KBIP6/SPSCK/ADP6 9 8 PTB3/KBIP7/MOSI/ADP7 PTB4/MISO 16-PIN ASSIGNMENT PDIP PTB4/MISO 16-PIN ASSIGNMENT TSSOP 1 PTB0/KBIP4/RxD/ADP4 12 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 PTB3/KBIP7/MOSI/ADP7 SS 16-PIN ASSIGNMENT QFN Figure 2-2. 16-Pin Packages PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/ADP1/ACMP– PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 PTB3/KBIP7/MOSI/ADP7 Freescale Semiconductor ...

Page 27

... Pin 1 indicator PTA4/ACMP0/BKGD/MS 1 PTB7/SCL/EXTAL PTB6/SDA/XTAL PTB5/TPMCH1/SS 2.2 Recommended System Connections Figure 2-4 shows pin connections that are common to almost all MC9S08QG8/4 application systems. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor PTA1/KBIP1/ADP1/ACMP‚ PTA2/KBIP2/SDA/ADP2 DD MC9S08QG8 PTA3/KBIP3/SCL/ADP3 PTB0/KBIP4/RxD/ADP4 5 14 PTB1/KBIP5/TxD/ADP5 6 13 PTB2/KBIP6/SPSCK/ADP6 ...

Page 28

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev MC9S08QG8 PORT XTAL NOTE 2 EXTAL NOTE 2 BKGD PORT B RESET/IRQ Figure 2-4. Basic System Connections PTA0/KBIP0/TPMCH0/ADP0/ACMP+ PTA1/KBIP1/ADP1/ACMP– PTA2/KBIP2/SDA/ADP2 PTA3/KBIP3/SCL/ADP3 PTA4/ACMPO/BKGD/MS PTA5/IRQ/TCLK/RESET I/O AND PERIPHERAL INTERFACE TO APPLICATION SYSTEM PTB0/KBIP4/RxD/ADP4 PTB1/KBIP5/TxD/ADP5 PTB2/KBIP6/SPSCK/ADP6 PTB3/KBIP7/MOSI/ADP7 PTB4/MISO PTB5/TPMCH1/SS PTB6/SDA/XTAL PTB7/SCL/EXTAL Freescale Semiconductor ...

Page 29

... The internal gates connected to this pin are pulled The RESET pullup should not be used to pull up components external to the MCU. In EMC-sensitive applications, an external RC filter is recommended on the RESET pin, if enabled. See MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 10, “Internal Clock Source (when used) and R should be low-inductance S F NOTE ...

Page 30

... After reset, the output-only port function is not enabled but is configured for low output drive strength with slew rate control enabled. The PTA4 pin defaults to BKGD/MS on any reset. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev 5.8.3, “System Background Debug Table 2-2. Chapter 6, “Parallel Freescale Semiconductor ...

Page 31

... DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of this, the EMC emissions may be affected by enabling pins as high drive. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 2 External Signal Description NOTE 29 ...

Page 32

... Alt 3 Alt 4 RESET BKGD EXTAL 2 XTAL SS ADP7 ADP6 ADP5 ADP4 2 ADP3 2 ADP2 3 3 ADP1 ACMP– ADP0 ACMP+ . The DD . The DD Reference Control” (S08ACMPV2)” (S08KBIV2)” (S08TPMV2)” (S08IICV1)” (S08ICSV1)” (S08ADC10V1)” Description” Freescale Semiconductor Control” ...

Page 33

... It is recommended that all modules that share a pin be disabled before enabling anther module. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 2 External Signal Description NOTE Table 2-1 shows the priority if multiple ...

Page 34

... Chapter 2 External Signal Description MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Freescale Semiconductor ...

Page 35

... Background Debug Force Reset Register • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a DBG breakpoint MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor (SBDFR)”) 33 ...

Page 36

... MCU is in wait mode. The memory-access-with-status commands do not allow memory access, but they report an error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used to wake the MCU from wait mode and enter active background mode. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Development Support chapter. Freescale Semiconductor ...

Page 37

... For the ADC to operate the LVD must be left enabled when entering stop3. 3.6.1.2 Active BDM Enabled in Stop Mode Entry into the active background mode from run mode is enabled if ENBDM in BDCSCR is set. This register is described in Chapter 17, “Development MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Table 3-1. Stop Mode Selection LVDSE PDC PPDC Stop modes disabled ...

Page 38

... PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev NOTE Table 3-1. Most is below the LVD DD Freescale Semiconductor ...

Page 39

... Peripheral CPU RAM FLASH Parallel Port Registers ADC ACMP ICS IIC MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE Section 3.6.1, “Stop3 Mode,” for specific information on Table 3-2. Stop Mode Behavior Mode Stop1 Stop2 Off Off Off ...

Page 40

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Table 3-2. Stop Mode Behavior (continued) Stop1 Off Off Off Off Off Standby Off Hi-Z States Held Mode Stop2 Stop3 Off Standby Off Standby Off Standby Off Standby Standby 3 Off Optionally On States Held Freescale Semiconductor ...

Page 41

... HIGH PAGE REGISTERS 0x184F 0x1850 UNIMPLEMENTED 51,120 BYTES 0xDFFF 0xE000 8192 BYTES 0xFFFF MC9S08QG8 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 0x0000 DIRECT PAGE REGISTERS 0x005F 0x0060 RAM 0x015F 512 BYTES 0x0160 0x025F 0x0260 5536 BYTES 0x17FF 0x1800 ...

Page 42

... Chapter 4 Memory Map and Register Definition 4.2 Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor-provided equate file for the MC9S08QG8/4. Address (High:Low) 0xFFC0:FFC1 0xFFCE:FFCF ...

Page 43

... KBEDG7 0x000F IRQSC 0 0x0010 ADCSC1 COCO 0x0011 ADCSC2 ADACT 0x0012 ADCRH 0 0x0013 ADCRL ADR7 Freescale Semiconductor can use the more efficient direct addressing mode that requires only Table 4-2. Direct-Page Register Summary PTAD5 PTAD4 0 PTADD5 PTADD4 PTBD6 PTBD5 PTBD4 PTBDD6 PTBDD5 PTBDD4 — ...

Page 44

... DATA — — — — — — — — — IREFS IRCLKEN IREFSTEN LP EREFS ERCLKEN EREFSTEN TRIM OSCINIT CLKST COUNT Freescale Semiconductor Bit 0 ADCV8 ADCV0 ADPC0 0 0 — — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 LSBFE SPC0 SPR0 0 0 Bit 0 — ...

Page 45

... Reserved — 0x180C SPMSC3 LVWF 0x180D– — Reserved 0x180F — 0x1810 DBGCAH Bit 15 0x1811 DBGCAL Bit 7 0x1812 DBGCBH Bit 15 0x1813 DBGCBL Bit 7 0x1814 DBGFH Bit 15 0x1815 DBGFL Bit 7 Freescale Semiconductor TOIE CPWMS CLKSB CH0IE MS0B MS0A CH1IE MS1B MS1A ...

Page 46

... PTASE3 PTASE2 PTASE1 PTADS3 PTADS2 PTADS1 — — — PTBPE3 PTBPE2 PTBPE1 PTBSE3 PTBSE2 PTBSE1 PTBDS3 PTBDS2 PTBDS1 — — — Freescale Semiconductor Bit 0 RWBEN TRG0 CNT0 — — SEC00 — 0 FPDIS 0 — — PTAPE0 PTASE0 PTADS0 — PTBPE0 PTBSE0 PTBDS0 ...

Page 47

... MC9S08QG8/ usually best to reinitialize the stack pointer to the top of the RAM so the direct page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX #RamLast+1 ...

Page 48

... FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev ...

Page 49

... Excluding start/end overhead If the COP is enabled during an erase function, make sure the COP is serviced during the erase command execution. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor (FCDIV)”). This register can be written only ) is used by the command processor to time FCLK = 1/f ...

Page 50

... FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev NOTE Figure 4 flowchart for executing all of the commands except for Freescale Semiconductor ...

Page 51

... A row of FLASH memory consists of 64 bytes. A byte within a row is selected by addresses A5 through A0. A new row begins when addresses A5 through A0 are all zero. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Note 1: Required only once after reset. WRITE TO FCDIV (Note 1) START ...

Page 52

... TO BUFFER ADDRESS AND DATA WRITE COMMAND (0x25) TO FCMD WRITE 1 TO FCBEF Note 2: Wait at least four bus cycles before TO LAUNCH COMMAND AND CLEAR FCBEF (Note 2) YES FPVIO OR FACCERR ? NO YES NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE checking FCBEF or FCCF. ERROR EXIT Freescale Semiconductor ...

Page 53

... FPS bits must be set to 1111 100, which results in the value 0xF9FF as the last address of unprotected memory. In addition to programming the FPS bits to the appropriate value, FPDIS (bit 0 of NVPROT) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 4 Memory Map and Register Definition NVPROT)”). ...

Page 54

... NVOPT location which can be done at the same time the FLASH memory is programmed. The 1:0 state disengages security and the other three combinations engage security. Notice the erased state (1:1) makes MC9S08QG8 and MC9S08QG4 Data Sheet, Rev A12 A11 A10 A9 A8 Figure 4-4. Block Protection Mechanism Freescale Semiconductor ...

Page 55

... Mass erase FLASH if necessary. 3. Blank check FLASH. Provided FLASH is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 4 Memory Map and Register Definition 53 ...

Page 56

... Refer to Table 4-3 and Table 4-4 section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 4.7.1 FLASH Clock Divider Register (FCDIV) Bit 7 of this register is a read-only status flag. Bits 6:0 may be read at any time but can be written only one time ...

Page 57

... SEC01:SEC00 changes to 1:0 after successful backdoor key entry or a successful blank check of FLASH. For more detailed information about security, refer to MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Table 4-7. FLASH Clock Divider Settings DIV f ...

Page 58

... Background commands can be used to change the contents of these bits in FPROT. Figure 4-8. FLASH Protection Register (FPROT) 56 Table 4-9. Security States SEC01:SEC00 Description 0:0 0:1 1:0 unsecured 1 KEYACC 0 0 Description Section 4. (1) FPS MC9S08QG8 and MC9S08QG4 Data Sheet, Rev secure secure secure “Security.” Freescale Semiconductor (1) FPDIS ...

Page 59

... Protection Violation Flag — FPVIOL is set automatically when FCBEF is cleared to register a command that FPVIOL attempts to erase or program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by writing FPVIOL protection violation attempt was made to erase or program a protected location. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Description 5 4 FPVIOL FACCERR 0 0 Figure 4-9 ...

Page 60

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Description Section 4.5.5, “Access Execution,” for a detailed discussion of FLASH FCMD Table 4-13. FLASH Commands FCMD Equate File Label 0x05 0x20 0x25 mBurstProg 0x40 mPageErase 0x41 mMassErase Errors.” FACCERR is cleared by Table 4-13. Refer mBlank mByteProg Freescale Semiconductor ...

Page 61

... Illegal opcode detect (ILOP) • Illegal address detect (ILAD) • Background debug force reset Each of these sources, with the exception of the background debug force reset, has an associated bit in the system reset status register. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Table 5-2) 59 ...

Page 62

... Clock Source COPT 0 ~1 kHz 1 ~1 kHz 0 Bus 1 Bus = 1 ms. See t RTI Timing,” for the tolerance of this value. Section 5.8.4, “System (SOPT2),” for additional COP Overflow Count cycles (32 ms cycles (256 ms cycles 18 2 cycles in the appendix RTI Freescale Semiconductor ...

Page 63

... RTI that is used to return from the ISR. When two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced first (see Table 5-2). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control NOTE 61 ...

Page 64

... ACCUMULATOR * INDEX REGISTER (LOW BYTE PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW ² ² TOWARD HIGHER ADDRESSES ² * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame 0 SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...

Page 65

... I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control NOTE and should not be driven DD ...

Page 66

... TOIE TPM overflow CH1IE TPM channel 1 CH0IE TPM channel 0 — — LVDIE Low-voltage detect IRQIE IRQ pin — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect RSTPE External pin — Illegal opcode — Illegal address — power-on-reset Freescale Semiconductor ...

Page 67

... Either RTI clock source can be used when the MCU is in run, wait or stop3 mode. When using the external oscillator in stop3, it must be enabled in stop (EREFSTEN = 1) and configured for low frequency operation MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control level. Both the POR bit and the LVD bit in SRS are set ...

Page 68

... Although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Section 5.8.7, “System Real-Time Interrupt Status and Control Chapter 4, “Memory Map and Register Operation.” Definition,” for the Freescale Semiconductor ...

Page 69

... IRQ Detection Mode — This read/write control bit selects either edge-only detection or edge-and-level IRQMOD detection. See Section 5.5.2.2, “Edge and Level 0 IRQ event on falling edges only. 1 IRQ event on falling edges and low levels. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control IRQF ...

Page 70

... Reset caused by LVD trip or POR COP ILOP ILAD Writing any value to SRS address clears COP watchdog timer (2) (2) Note Note Note Figure 5-3. System Reset Status (SRS) Table 5-4. SRS Register Field Descriptions Description MC9S08QG8 and MC9S08QG4 Data Sheet, Rev LVD ( Freescale Semiconductor ...

Page 71

... Writing 1 to this bit forces an MCU reset. This bit cannot be written from a user program. To enter user mode, PTA4/ACMPO/BKGD/MS must be high immediately after issuing WRITE_BYTE command. To enter BDM, PTA4/ACMPO/BKGD/MS must be low immediately after issuing WRITE_BYTE command. See Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 5 4 ...

Page 72

... MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET. 0 PTA5/IRQ/TCLK/RESET pin functions as PTA5, IRQ, or TCLK. 1 PTA5/IRQ/TCLK/RESET pin functions as RESET STOPE Table 5-6. SOPT1 Register Field Descriptions Description MC9S08QG8 and MC9S08QG4 Data Sheet, Rev BKGDPE Freescale Semiconductor 0 RSTPE ( ...

Page 73

... SDA on PTB6, SCL on PTB7. 0 Analog Comparator to Input Capture Enable— This bit connects the output of ACMP to TPM input channel 0. ACIC 0 ACMP output not connected to TPM input channel 0. 1 ACMP output connected to TPM input channel 0. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ...

Page 74

... Part Identification Number — Each derivative in the HCS08 Family has a unique identification number. The ID[7:0] MC9S08QG8 is hard coded to the value 0x009. See also ID bits in MC9S08QG8 and MC9S08QG4 Data Sheet, Rev ID11 — — 0 Description ID5 ID4 ID3 Description 2 1 ID10 ID9 ID8 0 0 Table 5- ID2 ID1 ID0 0 0 Table 5-8. Freescale Semiconductor ...

Page 75

... The initial RTI timeout period will one 1-kHz clock period less than the time specified the period of the external crystal frequency. ext MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control RTICLKS RTIE ...

Page 76

... Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the BGBE ADC module on one of its internal channels voltage reference for ACMP module. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled LVDIE LVDRE LVDSE 0 1 Description MC9S08QG8 and MC9S08QG4 Data Sheet, Rev LVDE Freescale Semiconductor 0 BGBE 0 ...

Page 77

... Partial Power Down Control — The PPDC bit controls which power down mode is selected. PPDC 0 Stop1 full power down mode enabled if PDC set. 1 Stop2 partial power down mode enabled if PDC set. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control PDF ...

Page 78

... Low trip point selected (V 1 High trip point selected ( LVDV LVWV transitions below the trip point or after reset and V Supply Description = V ). LVD LVDL = V ). LVD LVDH = V ). LVW LVWL = V ). LVW LVWH MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Unaffected by reset is already below V Supply ). LVD ). LVW Freescale Semiconductor LVW ...

Page 79

... The parallel I/O port function for an individual pin is illustrated in the block diagram shown in MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Description,” for more information about pin Table 1-1 for the number of general-purpose pins available on your ...

Page 80

... I/O registers. These registers are used to control pullups, slew rate, and drive strength for the pins. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...

Page 81

... Reset Reads of bit PTAD5 always return the pin value of PTA5, regardless of the value stored in bit PTADD5. 2 Reads of bit PTAD4 always return the contents of PTAD4, regardless of the value stored in bit PTADD4. Freescale Semiconductor Definition,” for the absolute address assignments PTAD5 PTAD4 ...

Page 82

... A pins independent of the parallel I/O register. 80 Table 6-1. PTAD Register Field Descriptions Description PTADD5 PTADD4 PTADD3 0 0 Table 6-2. PTADD Register Field Descriptions Description MC9S08QG8 and MC9S08QG4 Data Sheet, Rev PTADD2 PTADD1 Freescale Semiconductor 0 PTADD0 0 ...

Page 83

... Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control PTASE[5:0] is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. Freescale Semiconductor PTAPE5 ...

Page 84

... PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port A bit n. 1 High output drive strength selected for port A bit PTADS5 PTADS4 PTADS3 0 0 Table 6-5. PTADS Register Field Descriptions Description MC9S08QG8 and MC9S08QG4 Data Sheet, Rev PTADS2 PTADS1 Freescale Semiconductor 0 PTADS0 0 ...

Page 85

... PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Definition,” for the absolute address assignments 5 4 PTBD5 ...

Page 86

... PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev PTBPE5 PTBPE4 PTBPE3 Description PTBSE5 PTBSE4 PTBSE3 Description PTBPE2 PTBPE1 PTBPE0 PTBSE2 PTBSE1 PTBSE0 Freescale Semiconductor ...

Page 87

... PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Low output drive strength selected for port B bit n. 1 High output drive strength selected for port B bit n. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor ...

Page 88

... Chapter 6 Parallel Input/Output Control MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Freescale Semiconductor ...

Page 89

... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several ...

Page 90

... For compatibility with the earlier M68HC05 Family forced to 0x00 during reset. Reset has no effect on the contents of X. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers Freescale Semiconductor ...

Page 91

... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) 89 ...

Page 92

... No carry out of bit 7 1 Carry out of bit 7 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description Freescale Semiconductor ...

Page 93

... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) 91 ...

Page 94

... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev Freescale Semiconductor ...

Page 95

... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) Resets, Interrupts, and System Configuration ...

Page 96

... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation MC9S08QG8 and MC9S08QG4 Data Sheet, Rev chapter for more details. Freescale Semiconductor ...

Page 97

... Software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the BGND opcode. When the program reaches this breakpoint address, the CPU is forced to active background mode rather than continuing the user program. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 7 Central Processor Unit (S08CPUV2) 95 ...

Page 98

... rpp prpp prpp 0 – – rpp 3 F4 rfp pprpp prpp rfwpp rfwpp 4 78 rfwp prfwpp rfwpp rfwpp 4 77 rfwp prfwpp 3 – – – – – – ppp Freescale Semiconductor Affect on CCR – – – – – – – ...

Page 99

... Branch if Interrupt Mask Clear ( BMI rel Branch if Minus ( BMS rel Branch if Interrupt Mask Set ( BNE rel Branch if Not Equal ( BPL rel Branch if Plus ( MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Operation Object Code DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) ...

Page 100

... AD rr ssppp rpppp pppp pppp – – – – – – rpppp rfppp prpppp 1 – – – – – – – 0 – – – rfwpp – – – rfwpp 4 7F rfwp prfwpp Freescale Semiconductor Affect on CCR ...

Page 101

... EOR #opr8i Exclusive OR Memory with Accumulator A ← (A ⊕ M) EOR opr8a EOR opr16a EOR oprx16,X EOR oprx8,X EOR ,X EOR oprx16,SP EOR oprx8,SP MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Operation Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 M ← (M)= $FF – (M) ...

Page 102

... AE prrfp pprrpp prrpp prrpp rpp prpp prpp 0 – – rpp 3 FE rfp pprpp prpp rfwpp rfwpp 4 78 rfwp prfwpp rfwpp rfwpp 4 74 rfwp prfwpp Freescale Semiconductor Affect on CCR – – – – – – – – – – 0 ...

Page 103

... ROL ,X ROL oprx8,SP ROR opr8a Rotate Right through Carry RORA RORX ROR oprx8,X b7 ROR ,X ROR oprx8,SP MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Operation Object Code DIR/DIR DIR/IX+ source IMM/DIR IX+/DIR INH M ← – (M) = $00 – (M) DIR INH X ← – (X) = $00 – (X) INH M ← ...

Page 104

... B7 dd wpp pwpp pwpp 3 0 – wpp ppwpp pwpp wwpp 5 0 – pwwpp pwwpp 2 – – 0 – – – 8E fp... wpp pwpp pwpp 3 0 – wpp ppwpp pwpp Freescale Semiconductor Affect on CCR – – – – – – – – ...

Page 105

... TSTA TSTX TST oprx8,X TST ,X TST oprx8,SP Transfer SP to Index Reg. TSX H:X ← (SP) + $0001 Transfer X (Index Reg. Low) to Accumulator TXA A ← (X) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Operation Object Code IMM DIR EXT IX2 IX1 IX SP2 SP1 INH ...

Page 106

... Pop (read) one byte from stack u Read vector from $FFxx (high byte first) v Write 8-bit operand w CCR Effects: Set or cleared – Not affected U Undefined Affect Cyc-by-Cyc on CCR Details – – – – – – – – 0 – – – 8F fp... Freescale Semiconductor ...

Page 107

... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 7-3. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...

Page 108

... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...

Page 109

... The ACMP module can be configured to connect the output of the analog comparator to TPM input capture channel 0 by setting ACIC in SOPT2. With ACIC set, the TPMCH0 pin is not available externally regardless of the configuration of the TPM module. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Section 5.8.8, “System Power Management Status and Control 1 Section A.5, “DC 107 ...

Page 110

... Table 1-1 for available functions on each device. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 BKGD/MS IRQ TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS SCL PTA3/KBIP3/SCL/ADP3 SDA PTA2/KBIP2/SDA/ADP2 4 4 PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 4 PTB7/SCL/EXTAL 4 PTB6/SDA/XTAL TPMCH0 TPMCH1 SS PTB5/TPMCH1/SS MISO PTB4/MISO MOSI PTB3/KBIP7/MOSI/ADP7 SPSCK PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 Freescale Semiconductor ...

Page 111

... ACMP in Active Background Mode When the microcontroller is in active background mode, the ACMP will continue to operate normally. 8.1.5 Block Diagram The block diagram for the analog comparator module is shown MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Analog Comparator (S08ACMPV2) Figure 8-2. 109 ...

Page 112

... Analog Comparator (S08ACMPV2) Internal Reference ACMP+ ACMP– Figure 8-2. Analog Comparator (ACMP) Block Diagram MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 110 Internal Bus ACBGS Status & Control ACME Register + Interrupt Control – Comparator ACMP INTERRUPT REQUEST ACIE ACF ACOPE ACMPO Freescale Semiconductor ...

Page 113

... ACMP registers.This section refers to registers and control bits only by their names and relative address offsets. Some MCUs may have more than one ACMP, so register names include placeholder characters to identify which ACMP is being referenced. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Table 8-1. Table 8-1. Signal Properties Function Inverting analog input to the ACMP ...

Page 114

... ACMOD 00 Encoding 0 — Comparator output falling edge 01 Encoding 1 — Comparator output rising edge 10 Encoding 2 — Comparator output falling edge 11 Encoding 3 — Comparator output rising or falling edge MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 112 ACO ACF ACIE Description ACOPE ACMOD Freescale Semiconductor ...

Page 115

... The comparator output can be read directly through ACO. The comparator output can be driven onto the ACMPO pin using ACOPE. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Analog Comparator (S08ACMPV2) 113 ...

Page 116

... Analog Comparator (S08ACMPV2) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 114 Freescale Semiconductor ...

Page 117

... Analog-to-Digital Converter (S08ADC10V1) 9.1 Introduction The 10-bit analog-to-digital converter (ADC successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. Figure 9-1 shows the MC9S08QG8/4 with the ADC module and pins highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 115 ...

Page 118

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 BKGD/MS IRQ TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS SCL PTA3/KBIP3/SCL/ADP3 SDA PTA2/KBIP2/SDA/ADP2 4 4 PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 4 PTB7/SCL/EXTAL 4 PTB6/SDA/XTAL TPMCH0 TPMCH1 SS PTB5/TPMCH1/SS MISO PTB4/MISO MOSI PTB3/KBIP7/MOSI/ADP7 SPSCK PTB2/KBIP6/SPSCK/ADP6 TxD PTB1/KBIP5/TxD/ADP5 RxD PTB0/KBIP4/RxD/ADP4 Freescale Semiconductor ...

Page 119

... Selecting the internal bandgap channel requires BGBE =1 in SPMSC1; see Section 5.8.8, “System Power Management Status and Control 1 Register (SPMSC1).” For the value of the bandgap voltage reference see Section A.5, “DC Freescale Semiconductor SS Table 9-1. ADC Channel Assignment Pin Control ...

Page 120

... The ADC is capable of running in stop3 mode but requires LVDSE and LVDE in SPMSC1 to be set. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 118 ) ÷ m) Temp = 25 - ((V -V TEMP TEMP25 and m values from TEMP25 , the cold slope value is applied in TEMP25 Equation 9-1. Eqn. 9-1 Section A.10, “ADC Characteristics,” , and compares to TEMP Equation 9- TEMP Freescale Semiconductor is ...

Page 121

... Asynchronous clock source for lower noise operation. • Selectable asynchronous hardware conversion trigger. • Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value. 9.1.3 Block Diagram Figure 9-2 provides a block diagram of the ADC module MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 119 ...

Page 122

... Figure 9-2. ADC Block Diagram Table 9-2. Signal Properties Name Function AD27–AD0 Analog Channel inputs V High reference voltage REFH V Low reference voltage REFL V Analog power supply DDAD V Analog ground SSAD Async Clock Gen ADACK Bus Clock ÷2 ALTCLK AIEN 1 Interrupt COCO 2 3 Freescale Semiconductor ...

Page 123

... This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1 aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other than all 1s). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor ) DDAD as its power connection. In some packages, V ...

Page 124

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 122 ADCO Description Figure 9-4. Figure 9-4. Input Channel Select Input Select AD0 AD1 AD2 AD3 AD4 AD5 AD6 ADCH ADCH Input Select 10000 AD16 10001 AD17 10010 AD18 10011 AD19 10100 AD20 10101 AD21 10110 AD22 Freescale Semiconductor ...

Page 125

... Two types of trigger are selectable: software trigger and hardware trigger. When software trigger is selected, a conversion is initiated following a write to ADCSC1. When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input. 0 Software trigger selected 1 Hardware trigger selected MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Input Select AD7 AD8 AD9 AD10 ...

Page 126

... In 8-bit mode, there is no interlocking with ADCRH. In the case that the MODE bits are changed, any data in ADCRL becomes invalid. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 124 Description ADR9 ADR8 Freescale Semiconductor ...

Page 127

... ADCV6 W Reset Figure 9-9. Compare Value Low Register(ADCCVL) 9.3.7 Configuration Register (ADCCFG) ADCCFG is used to select the mode of operation, clock source, clock divide, and configure for low power or long sample time. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor ADR5 ADR4 ADR3 ...

Page 128

... Description Table 9-6. Clock Divide Select Divide Ratio Table 9-7. Conversion Modes Mode Description 8-bit conversion (N=8) Reserved 10-bit conversion (N=10) Reserved MODE ADICLK Table Clock Rate Input clock Input clock ÷ 2 Input clock ÷ 4 Input clock ÷ 8 Freescale Semiconductor 9-7. ...

Page 129

... ADC Pin Control 2 — ADPC2 is used to control the pin associated with channel AD2. ADPC2 0 AD2 pin I/O control enabled 1 AD2 pin I/O control disabled MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Table 9-8. Input Clock Select Selected Clock Source Bus clock Bus clock divided by 2 ...

Page 130

... ADC Pin Control 10 — ADPC10 is used to control the pin associated with channel AD10. ADPC10 0 AD10 pin I/O control enabled 1 AD10 pin I/O control disabled MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 128 Description ADPC13 ADPC12 ADPC11 Description ADPC10 ADPC9 ADPC8 Freescale Semiconductor ...

Page 131

... AD19 pin I/O control disabled 2 ADC Pin Control 18 — ADPC18 is used to control the pin associated with channel AD18. ADPC18 0 AD18 pin I/O control enabled 1 AD18 pin I/O control disabled MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Description ADPC21 ADPC20 ADPC19 ...

Page 132

... Whichever clock is selected, its frequency must fall within the specified frequency range for ADCK. If the available clocks are too slow, the ADC will not perform according to specifications. If the available clocks MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 130 Description Freescale Semiconductor ...

Page 133

... In software triggered operation, continuous conversions begin after ADCSC1 is written and continue until aborted. In hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) 131 ...

Page 134

... ADLSMP is used to select between short and long sample times.When sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. The MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 132 ). After f ADCK Freescale Semiconductor ...

Page 135

... MHz, then the conversion time for a single conversion is: Conversion time = Number of bus cycles = 3.5 μ MHz = 28 cycles The ADCK frequency must be between f maximum to meet ADC specifications. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor frequency, precise sample time for continuous conversions ADCK ADICLK ADLSMP 0x, 10 ...

Page 136

... If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a STOP instruction aborts the current conversion and places the ADC in its idle state. The contents of ADCRH and ADCRL are unaffected by stop3 mode.After exiting from stop3 mode, a software or hardware trigger is required to resume conversions. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 134 NOTE Freescale Semiconductor ...

Page 137

... Update the configuration register (ADCCFG) to select the input clock source and the divide ratio used to generate the internal clock, ADCK. This register is also used for selecting sample time and low-power configuration. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE Conversions) is cleared when entering stop3 Table ...

Page 138

... Software trigger selected Compare function disabled Not used in this example Unimplemented or reserved, always reads zero Reserved for Freescale’s internal use; always write zero Read-only flag which is set when a conversion completes Conversion complete interrupt enabled One conversion only (continuous conversions disabled) Freescale Semiconductor ...

Page 139

... When available on a separate pin, both V as their corresponding MCU digital supply (V noise immunity and bypass capacitors placed as near as possible to the package. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor RESET INITIALIZE ADC ADCCFG = $98 ADCSC2 = $00 ...

Page 140

... The input is sampled for on some devices. The low DDAD on some devices may be DDAD spec and the V potential (V DDAD must be connected to the same REFL . Setting the pin control register bits for and the input is equal to or REFL , the converter circuit converts it REFL Freescale Semiconductor REFH ...

Page 141

... I/O activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: Place a 0.01 μF capacitor (C • improve noise issues but will affect sample rate based on the external analog source resistance). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor lower than REFH REFL ...

Page 142

... Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 140 LSB REFH REFL ). Note, if the last conversion is $3FE, then the LSB , one-time error. LSB Eqn. 9-2 . LSB ). Note, if the first LSB LSB ) is used. LSB Freescale Semiconductor ) is ...

Page 143

... Missing codes are those values which are never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and to have no missing codes. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Analog-to-Digital Converter (S08ADC10V1) and will increase with noise. This error may be ...

Page 144

... Analog-to-Digital Converter (S08ADC10V1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 142 Freescale Semiconductor ...

Page 145

... FLASH memory to the ICSTRM register. A factory value for this FTRIM bit is also stored in FLASH and must be copied into the FTRIM bit in the ICSSC register. See the factory ICSTRM and FTRIM values. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor NOTE Table 1-1 Table 4-4 ...

Page 146

... Table 1-1 for available functions on each device. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 BKGD/MS IRQ TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS SCL PTA3/KBIP3/SCL/ADP3 SDA PTA2/KBIP2/SDA/ADP2 4 4 PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 4 PTB7/SCL/EXTAL 4 PTB6/SDA/XTAL TPMCH0 TPMCH1 SS PTB5/TPMCH1/SS MISO PTB4/MISO MOSI PTB3/KBIP7/MOSI/ADP7 SPSCK PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 Freescale Semiconductor ...

Page 147

... In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock derived from the internal reference clock. The BDC clock is not available. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor l (FEI) (FEE) l (FBI) l Low Power (FBILP) ...

Page 148

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 146 l (FBE) l Low Power (FBELP) Optional EREFS EREFSTEN Block ERCLKEN IRCLKEN IREFSTEN CLKS Internal LP Reference Clock DCOOUT 9 DCO TRIM 9 n RDIV_CLK Filter FLL Internal Clock Source Block ICSERCLK ICSIRCLK BDIV ICSOUT n=0-3 ICSLCLK / 2 ICSFFCLK Freescale Semiconductor ...

Page 149

... ICS enters stop mode. 1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode before entering stop 0 Internal reference clock is disabled in stop MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 5 4 RDIV 0 0 Figure 10-3 ...

Page 150

... External reference clock stays enabled in stop if ERCLKEN is set or if ICS is in FEE, FBE, or FBELP mode before entering stop 0 External reference clock is disabled in stop MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 148 5 4 RANGE HGO 0 0 Figure 10-4. ICS Control Register 2 (ICSC2) Description EREFS ERCLKEN EREFSTEN Freescale Semiconductor 0 0 ...

Page 151

... ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency. 0 Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor TRIM ...

Page 152

... Figure 10-7. Clock Switching Modes IREFS=1 CLKS=01 BDM Enabled or LP=0 FLL Bypassed FLL Bypassed Internal Low Internal (FBI) Power(FBILP) IREFS=1 CLKS=01 BDM Disabled and LP=1 Returns to state that was active before MCU entered stop, unless RESET occurs while in stop. Freescale Semiconductor ...

Page 153

... In FLL bypassed external mode, the ICSOUT clock is derived from the external reference clock. The FLL clock is controlled by the external reference clock, and the FLL loop will lock the FLL frequency to 512 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Internal Clock Source (S08ICSV1) 151 ...

Page 154

... If the newly selected clock is not available, the previous clock will remain selected. 10.4.3 Bus Frequency Divider The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur immediately. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 152 Freescale Semiconductor ...

Page 155

... In FLL engaged mode (FEI and FEE), this is always true and ICSFFE is always high. In ICS Bypass modes, ICSFFE will get asserted for the following combinations of BDIV and RDIV values: MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Internal Clock Source (S08ICSV1) Device ...

Page 156

... Internal Clock Source (S08ICSV1) BDIV=00 (divide by 1), RDIV ≥ 010 • BDIV=01 (divide by 2), RDIV ≥ 011 • BDIV=10 (divide by 4), RDIV ≥ 100 • BDIV=11 (divide by 8), RDIV ≥ 101 • MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 154 Freescale Semiconductor ...

Page 157

... IICPS in SOPT2 selects which general-purpose I/O ports are associated with IIC operation. IICPS in SOPT2 0 (default) 1 Figure 11-1 is the MC9S08QG8/4 block diagram with the IIC block highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Table 11-1. IIC Position Options Port Pin for SDA PTA2 PTB6 Port Pin for SCL PTA3 PTB7 ...

Page 158

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 BKGD/MS IRQ TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS SCL PTA3/KBIP3/SCL/ADP3 SDA PTA2/KBIP2/SDA/ADP2 4 4 PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 4 PTB7/SCL/EXTAL 4 PTB6/SDA/XTAL TPMCH0 TPMCH1 SS PTB5/TPMCH1/SS MISO PTB4/MISO MOSI PTB3/KBIP7/MOSI/ADP7 SPSCK PTB2/KBIP6/SPSCK/ADP6 TxD PTB1/KBIP5/TxD/ADP5 RxD PTB0/KBIP4/RxD/ADP4 Freescale Semiconductor ...

Page 159

... Stop mode — The IIC is inactive in stop3 mode for reduced power consumption. The STOP instruction does not affect IIC register states. Stop2 will reset the register contents. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) 157 ...

Page 160

... This section consists of the IIC register descriptions in address order. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 158 FREQ_REG ADDR_REG STATUS_REG START STOP ARBITRATION CONTROL SCL SDA Figure 11-2. IIC Functional Block Diagram DATA BUS INTERRUPT DATA_MUX DATA_REG IN/OUT DATA SHIFT REGISTER ADDRESS COMPARE Freescale Semiconductor ...

Page 161

... R MULT W Reset 0 0 Figure 11-4. IIC Frequency Divider Register (IICF) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Memory chapter of this data sheet for the absolute address 5 4 ADDR 0 0 Figure 11-3. IIC Address Register (IICA) Table 11-2. IICA Register Field Descriptions ...

Page 162

... SDA hold time = 1/8000000 * 9 = 1.125 μs If the generated SDA hold value is not acceptable, the MULT bits can be used to change the ICR. This will result in a different SDA hold value. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 160 Table 11-3. IICF Register Field Descriptions Description Freescale Semiconductor ...

Page 163

... ICR SCL Divider (hex 104 17 128 112 1B 128 1C 144 1D 160 1E 192 1F 240 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Table 11-4. IIC Divider and Hold Values SDA Hold ICR Value (hex Inter-Integrated Circuit (S08IICV1) SDA Hold SCL Divider Value 160 ...

Page 164

... This bit will always be read as a low. Attempting a repeat at the wrong time will result in loss of arbitration. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 162 5 4 MST TX TXAK 0 0 Figure 11-5. IIC Control Register (IICC) Table 11-5. IICC Register Field Descriptions Description RSTA Freescale Semiconductor ...

Page 165

... Receive Acknowledge — When the RXAK bit is low, it indicates an acknowledge signal has been received after RXAK the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge signal is detected. 0 Acknowledge received acknowledge received. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 5 4 BUSY ARBL 0 0 Figure 11-6 ...

Page 166

... R/W bit (in position bit 0). MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 164 5 4 DATA 0 0 Figure 11-7. IIC Data I/O Register (IICD) Table 11-7. IICD Register Field Descriptions Description NOTE Freescale Semiconductor 0 0 ...

Page 167

... AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W CALLING ADDRESS START SIGNAL MSB SCL SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W START CALLING ADDRESS SIGNAL MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor LSB MSB XXX READ/ ACK BIT WRITE LSB ...

Page 168

... Relinquishes the bus by generating a STOP signal. • Commences a new calling by generating a repeated START signal. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 166 11-8. There is one clock pulse on SCL for each data bit, the MSB being Figure 11-8, a Figure 11-8). Freescale Semiconductor ...

Page 169

... There is then no difference between the device clocks and the state of the SCL line and all the devices start counting their high periods. The first device to complete its high period pulls the SCL line low again. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) Figure 11-9). When all ...

Page 170

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 168 DELAY Figure 11-9. IIC Clock Synchronization Table 11-8. Interrupt Summary Status TCF IAAS ARBL START COUNTING HIGH PERIOD Table 11-8 occur provided the IICIE bit Flag Local Enable IICIF IICIE IICIF IICIE IICIF IICIE Freescale Semiconductor ...

Page 171

... A START cycle is attempted when the bus is busy. • A repeated START cycle is requested in slave mode. • A STOP condition is detected when the master did not request it. This bit must be cleared by software by writing a one to it. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Inter-Integrated Circuit (S08IICV1) 169 ...

Page 172

... Figure 11-11 Module Initialization (Master) Figure 11-11 Module Use can handle both master and slave IIC operations. For slave operation, an Register Model ADDR ICR MST TX TXAK RSTA BUSY ARBL 0 SRW DATA Figure 11-10. IIC Module Quick Start IICIF RXAK Freescale Semiconductor ...

Page 173

... Y Addr Cycle (Master Rx Write Next Set TXACK =1 Byte to IICD Switch to Rx Mode Generate Dummy Read Stop Signal from IICD (MST = 0) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Clear IICIF Master Y Mode ? RX Last Byte to Be Read 2nd Last (Read) Y Byte to Be Read ...

Page 174

... Inter-Integrated Circuit (S08IICV1) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 172 Freescale Semiconductor ...

Page 175

... Chapter 12 Keyboard Interrupt (S08KBIV2) 12.1 Introduction The keyboard interrupt KBI module provides up to eight independently enabled external interrupt sources. Figure 12-1 Shows the MC9S08QG8/4 block guide with the KBI highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 173 ...

Page 176

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 BKGD/MS IRQ TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS SCL PTA3/KBIP3/SCL/ADP3 SDA PTA2/KBIP2/SDA/ADP2 4 4 PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 4 PTB7/SCL/EXTAL 4 PTB6/SDA/XTAL TPMCH0 TPMCH1 SS PTB5/TPMCH1/SS MISO PTB4/MISO MOSI PTB3/KBIP7/MOSI/ADP7 SPSCK PTB2/KBIP6/SPSCK/ADP6 TxD PTB1/KBIP5/TxD/ADP5 RxD PTB0/KBIP4/RxD/ADP4 Freescale Semiconductor ...

Page 177

... When the microcontroller is in active background mode, the KBI will continue to operate normally. 12.1.3 Block Diagram The block diagram for the keyboard interrupt module is shown MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Keyboard Interrupts (S08KBIV2) Modes of Operation Figure 12-2. 175 ...

Page 178

... KBACK V RESET DD CLR KEYBOARD INTERRUPT FF KBMOD Figure 12-2. KBI Block Diagram Table 12-1. Table 12-1. Signal Properties Function Keyboard interrupt pins Memory chapter for the absolute address assignments for BUSCLK KBF SYNCHRONIZER STOP BYPASS STOP KBI INTERRU PT KBIE I/O I Freescale Semiconductor ...

Page 179

... Keyboard Pin Enables — Each of the KBIPEn bits enable the corresponding keyboard interrupt pin. KBIPEn 0 Pin not enabled as keyboard interrupt. 1 Pin enabled as keyboard interrupt. 12.3.3 KBI Edge Select Register (KBIES) KBIES contains the edge select control bits. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor KBF 0 ...

Page 180

... A valid edge or level on an enabled KBI pin will set KBF in KBISC. If KBIE in KBISC is set, an interrupt request will be presented to the CPU. Clearing of KBF is accomplished by writing KBACK in MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 178 KBEDG5 KBEDG4 KBEDG3 Figure 12-5. KBI Edge Select Register Description KBEDG2 KBEDG1 KBEDG0 Freescale Semiconductor ...

Page 181

... If using internal pullup/pulldown device, configure the associated pullup enable bits in PTxPE. 4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE. 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Keyboard Interrupts (S08KBIV2) 179 ...

Page 182

... Keyboard Interrupts (S08KBIV2) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 180 Freescale Semiconductor ...

Page 183

... The external clock for the MTIM module, TCLK, is selected by setting CLKS = 1:1 or 1:0 in MTIMCLK, which selects the TCLK pin input. The TCLK input on PTA5 can be enabled as external clock inputs to both the MTIM and TPM modules simultaneously. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 181 ...

Page 184

... Table 1-1 for available functions on each device. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 BKGD/MS IRQ TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS SCL PTA3/KBIP3/SCL/ADP3 SDA PTA2/KBIP2/SDA/ADP2 4 4 PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 4 PTB7/SCL/EXTAL 4 PTB6/SDA/XTAL TPMCH0 TPMCH1 SS PTB5/TPMCH1/SS MISO PTB4/MISO MOSI PTB3/KBIP7/MOSI/ADP7 SPSCK PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 Freescale Semiconductor ...

Page 185

... The MTIM suspends all counting until the microcontroller returns to normal user operating mode. Counting resumes from the suspended value as long as an MTIM reset did not occur (TRST written MOD written). MTIM MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Modulo Timer (S08MTIMV1) 183 ...

Page 186

... Figure PRESCALE CLOCK AND SELECT SOURCE DIVIDE BY SELECT CLKS PS Table 13-1. Signal Properties Function External clock source input into MTIM 13-2. 8-BIT COUNTER (MTIMCNT) 8-BIT COMPARATOR 8-BIT MODULO (MTIMMOD) Table 13-1. I/O I Pins and Connections chapter for Freescale Semiconductor TRST TSTP ...

Page 187

... MTIM registers.This section refers to registers and control bits only by their names and relative address offsets. Some MCUs may have more than one MTIM, so register names include placeholder characters to identify which MTIM is being referenced. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Figure 13-3. Register Summary MTIM 7 ...

Page 188

... MTIM Counter Stop — When set, this read/write bit stops the MTIM counter at its current value. Counting resumes TSTP from the current value when TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting. 0 MTIM counter is active. 1 MTIM counter is stopped. 3:0 Unused register bits, always read 0. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 186 TSTP TRST Description Freescale Semiconductor ...

Page 189

... Encoding 5. MTIM clock source ÷ 32 0110 Encoding 6. MTIM clock source ÷ 64 0111 Encoding 7. MTIM clock source ÷ 128 1000 Encoding 8. MTIM clock source ÷ 256 All other encodings default to MTIM clock source ÷ 256. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor CLKS 0 ...

Page 190

... MTIM in free-running mode. Writing to MTIMMOD resets the COUNT to $00 and clears TOF. Reset sets the modulo to $00. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 188 COUNT Figure 13-6. MTIM Counter Register Description MOD Figure 13-7. MTIM Modulo Register Modulo Register Field Descriptions MTIM Description Freescale Semiconductor ...

Page 191

... MTIM overflow interrupt enable bit (TOIE) in written while TOF = 1. Instead, TOF should be cleared first, then the TOIE can be set to 1. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor SC are used to select the desired clock source. If the counter is MTIM SC select the desired prescale value ...

Page 192

... The timer overflow flag, TOF, sets when the counter value changes from $AA to $00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 190 $A8 $A9 $AA $AA $00 $01 MOD register is set to $AA. MTIM Freescale Semiconductor ...

Page 193

... Chapter 14 Serial Communications Interface (S08SCIV3) 14.1 Introduction Figure 14-1 shows the MC9S08QG8/4 block diagram with the SCI highlighted. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor 191 ...

Page 194

... Table 1-1 for available functions on each device. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 BKGD/MS IRQ TCLK PTA5//IRQ/TCLK/RESET PTA4/ACMPO/BKGD/MS SCL PTA3/KBIP3/SCL/ADP3 SDA PTA2/KBIP2/SDA/ADP2 4 4 PTA1/KBIP1/ADP1/ACMP– PTA0/KBIP0/TPMCH0/ADP0/ACMP+ 4 PTB7/SCL/EXTAL 4 PTB6/SDA/XTAL TPMCH0 TPMCH1 SS PTB5/TPMCH1/SS MISO PTB4/MISO MOSI PTB3/KBIP7/MOSI/ADP7 SPSCK PTB2/KBIP6/SPSCK/ADP6 PTB1/KBIP5/TxD/ADP5 PTB0/KBIP4/RxD/ADP4 Freescale Semiconductor ...

Page 195

... T8 SCIS3 9th data bits R7/T7 R6/T6 SCIID Read: Rx data; write: Tx data MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Chapter 14 Serial Communications Interface (S08SCIV3) Module Initialization: to set baud rate to configure 1-wire/2-wire, 9/8-bit data, wakeup, and parity, if used. to configure interrupts, enable Rx and Tx, RWU ...

Page 196

... Section 14.3, “Functional Description,” for a detailed description of SCI operation in the different modes. • 8- and 9- bit data modes • Stop modes — SCI is halted during all stop modes • Loop mode • Single-wire mode MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 194 Freescale Semiconductor ...

Page 197

... Block Diagram Figure 14-3 shows the transmitter portion of the SCI. INTERNAL BUS M 1 × BAUD RATE CLOCK SBK TXDIR BRK13 MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor (Figure 14-4 (WRITE-ONLY) SCID – Tx BUFFER 11-BIT TRANSMIT SHIFT REGISTER SHIFT DIRECTION T8 ...

Page 198

... MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 196 (READ-ONLY) SCID – Rx BUFFER DIVIDE 11-BIT RECEIVE SHIFT REGISTER WAKE WAKEUP LOGIC ILT RDRF RIE IDLE ILIE OR ORIE FE FEIE NF NEIE PARITY PF CHECKING PEIE Figure 14-4. SCI Receiver Block Diagram SHIFT DIRECTION RWU Rx INTERRUPT REQUEST ERROR INTERRUPT REQUEST Freescale Semiconductor ...

Page 199

... When 8191, the SCI baud rate = BUSCLK/(16×BR). See also BR bits SBR7 SBR6 W Reset 0 0 Figure 14-6. SCI Baud Rate Register (SCIBDL) MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 Freescale Semiconductor Memory chapter of this data sheet for the absolute address SBR12 SBR11 ...

Page 200

... Idle character bit count starts after stop bit. MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5 198 Description 5 4 RSRC M WAKE 0 0 Figure 14-7. SCI Control Register 1 (SCIC1) Description Section 14.3.3.2, “Receiver Wakeup Wakeup” for more information. Table 14- ILT Operation” for more Freescale Semiconductor ...

Related keywords