mm74hct245 Fairchild Semiconductor, mm74hct245 Datasheet

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mm74hct245

Manufacturer Part Number
mm74hct245
Description
Mm74hct245 Octal 3-state Transceiver
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2005 Fairchild Semiconductor Corporation
MM74HCT245WM
MM74HCT245SJ
MM74HCT245MTC
MM74HCT245N
MM74HCT245
Octal 3-STATE Transceiver
General Description
The MM74HCT245 3-STATE bi-directional buffer utilizes
advanced silicon-gate CMOS technology and is intended
for two-way asynchronous communication between data
buses. It has high drive current outputs which enable high
speed operation even when driving large bus capaci-
tances. This circuit possesses the low power consumption
of CMOS circuitry, yet has speeds comparable to low
power Schottky TTL circuits.
This device is TTL input compatible and can drive up to 15
LS-TTL loads, and all inputs are protected from damage
due to static discharge by diodes to V
The MM74HCT245 has one active low enable input (G),
and a direction control (DIR). When the DIR input is HIGH,
data flows from the A inputs to the B outputs. When DIR is
LOW, data flows from B to A.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power consumption in
existing designs.
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Order Number
Pin Assignments for DIP, SOIC, SOP and TSSOP
Package Number
Top View
MTC20
M20B
M20D
N20A
CC
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
and ground.
DS005366
Features
Truth Table
H
L
X
TTL input compatible
3-STATE outputs for connection to system busses
High output drive current: 6 mA (min)
High speed: 16 ns typical propagation delay
Low power: 80
LOW Level
Irrelevant
HIGH Level
Package Description
G
H
L
L
Control
Inputs
P
A (74HCT Series)
DIR
H
L
X
February 1984
Revised May 2005
B data to A bus
A data to B bus
Operation
isolation
www.fairchildsemi.com
245

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mm74hct245 Summary of contents

Page 1

... LS-TTL loads, and all inputs are protected from damage due to static discharge by diodes to V and ground. CC The MM74HCT245 has one active low enable input (G), and a direction control (DIR). When the DIR input is HIGH, data flows from the A inputs to the B outputs. When DIR is LOW, data flows from ...

Page 2

Logic Diagram www.fairchildsemi.com 2 ...

Page 3

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Clamp Diode Current ( Output Current GND ...

Page 4

AC Electrical Characteristics q V 5.0V ns (unless otherwise specified Symbol Parameter Maximum Output PHL PLH Propagation Delay Maximum Output PZL PZH Enable Time ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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