mm74hct541 Fairchild Semiconductor, mm74hct541 Datasheet
mm74hct541
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mm74hct541 Summary of contents
Page 1
... NOR such that if either are HIGH, all eight outputs are in the high-impedance state. In order to enhance PC board layout, the MM74HCT540 and MM74HCT541 offers a pinout having inputs and outputs on opposite sides of the package. All inputs are protected from damage due to static discharge by diodes to V and ground ...
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... Connection Diagrams Pin Assignments for DIP, SOIC, SOP and TSSOP ©1984 Fairchild Semiconductor Corporation Rev. 1.3 Top View, MM74HCT540 Top View, MM74HCT541 2 www.fairchildsemi.com ...
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... Symbol V Supply Voltage Input or Output Voltage IN OUT T Operating Temperature Range Input Rise and Fall Times r f ©1984 Fairchild Semiconductor Corporation Rev. 1.3 (1) Parameter Parameter 3 Rating –0.5 to +7.0V –1 +1.5V CC –0 +0.5V CC ±20mA ±35mA ±70mA –65°C to +150°C ...
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... Voltage V Maximum LOW OL Level Voltage I Maximum Input IN Current I Maximum 3-STATE OZ Output Leakage Current I Maximum CC Quiescent Supply Current Note: 3. Measured per input. All other inputs at V ©1984 Fairchild Semiconductor Corporation Rev. 1 Conditions Typ 20µA V OUT 6.0mA ...
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... Capacitance C Maximum Output OUT Capacitance C Power Dissipation PD (4) Capacitance Note determines the no load dynamic power consumption current consumption ©1984 Fairchild Semiconductor Corporation Rev. 1.3 t 6ns, T 25°C, (unless otherwise specified Conditions C 45pF L C 45pF 5pF 6ns (unless otherwise specified) ...
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... Maximum Output Propagation Delay PHL PLH Maximum Output Enable Time PZL PZH Maximum Output Disable Time PLZ PHZ AC Electrical Characteristics MM74HCT541: V 5.0V ± 10 Symbol Parameter Maximum Output PHL PLH Propagation Delay Maximum Output PZH PZL Enable Time ...
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... Physical Dimensions Dimensions are in inches (millimeters) unless otherwise noted. Figure 1. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide ©1984 Fairchild Semiconductor Corporation Rev. 1.3 Package Number M20B 7 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 2. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide ©1984 Fairchild Semiconductor Corporation Rev. 1.3 Package Number M20D 8 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in millimeters unless otherwise noted. Figure 3. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide ©1984 Fairchild Semiconductor Corporation Rev. 1.3 Package Number MTC20 9 www.fairchildsemi.com ...
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... Physical Dimensions (Continued) Dimensions are in inches (millimeters) unless otherwise noted. Figure 4. 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide ©1984 Fairchild Semiconductor Corporation Rev. 1.3 Package Number N20A 10 www.fairchildsemi.com ...
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... TRADEMARKS The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended exhaustive list of all such trademarks ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...