MPC9239 Motorola Semiconductor Products, MPC9239 Datasheet
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MPC9239
Manufacturer Part Number
MPC9239
Description
900 MHZ Low Voltage Pecl Clock Synthesizer
Manufacturer
Motorola Semiconductor Products
Datasheet
1.MPC9239.pdf
(12 pages)
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
900 MHz Low Voltage
LVPECL Clock Synthesizer
targeted for high performance clock generation in mid-range to
high-performance telecom, networking and computing applications. With
output frequencies from 3.125 MHz to 900 MHz and the support of
differential LVPECL output signals the device meets the needs of the
most demanding clock applications.
Features
Functional Description
internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a range
of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal
oscillator frequency f XTAL , the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock.
The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must be
programmed by the serial or parallel interface.
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this
document. The configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input.
See the programming section for more information. The TEST output reflects various internal node values, and is controlled by
the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST
output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked
by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the
PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
3.125 MHz to 900 MHz synthesized clock output signal
Differential LVPECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference input
3.3V power supply
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
28 PLCC and 32 LQFP packaging
SiGe Technology
Ambient temperature range 0 C to + 70 C
Pin and function compatible to the MC12439
The MPC9239 is a 3.3V compatible, PLL based clock synthesizer
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]
Motorola, Inc. 2003
900 MHZ LOW VOLTAGE
CLOCK SYNTHESIZER
28–LEAD PLCC PACKAGE
32 LEAD LQFP PACKAGE
MPC9239
CASE 873A
FN SUFFIX
FA SUFFIX
CASE 776
Order Number: MPC9239/D
to V CC – 2.0V. The
Rev 2, 03/2003