XC9536-15 XILINX [Xilinx, Inc], XC9536-15 Datasheet

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XC9536-15

Manufacturer Part Number
XC9536-15
Description
XC9536 In-System Programmable CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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9
December 4, 1998 (Version 5.0)
Features
• 5 ns pin-to-pin logic delays on all pins
• f
• 36 macrocells with 800 usable gates
• Up to 34 user I/O pins
• 5 V in-system programmable (ISP)
• Enhanced pin-locking architecture
• Flexible 36V18 Function Block
• Extensive IEEE Std 1149.1 boundary-scan (JTAG)
• Programmable power reduction mode in each
• Slew rate control on individual outputs
• User programmable ground pin capability
• Extended pattern security features for design protection
• High-drive 24 mA outputs
• 3.3 V or 5 V I/O capability
• Advanced CMOS 5V FastFLASH technology
• Supports parallel programming of more than one
• Available in 44-pin PLCC, 44-pin VQFP, and 48-pin
Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See
ture overview.
December 4, 1998 (Version 5.0)
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
- 90 product terms drive any or all of 18 macrocells
- Global and product term clocks, output enables, set
support
macrocell
XC9500 concurrently
CSP packages
CNT
temperature range
within Function Block
and reset signals
to 100 MHz
Figure 2
for the architec-
1
1
1*
XC9536 In-System Programmable
CPLD
Product Specification
Power Management
Power dissipation can be reduced in the XC9536 by config-
uring macrocells to standard or low-power modes of opera-
tion. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
MC
Where:
MC
MC
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1
Figure 1: Typical I
CC
HP
HP
LP
(mA) =
(50)
(30)
= Macrocells in low-power mode
(1.7) + MC
= Macrocells in high-performance mode
shows a typical calculation for the XC9536 device.
0
LP
(0.9) + MC (0.006 mA/MHz) f
CC
Clock Frequency (MHz)
vs. Frequency For XC9536
50
100
X5920
(83)
(50)
1

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XC9536-15 Summary of contents

Page 1

... CPLD Product Specification 1 1* Power Management Power dissipation can be reduced in the XC9536 by config- uring macrocells to standard or low-power modes of opera- tion. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: ...

Page 2

... XC9536 In-System Programmable CPLD 1 JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Figure 2: XC9536 Architecture Note: Function Block outputs (indicated by the bold line) drive the I/O Blocks directly 2 3 JTAG Controller I/O Blocks In-System Programming Controller 36 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells X5919 ...

Page 3

... High-level input voltage IH V Output voltage O Note 1. Numbers in parenthesis are for industrial-temperature range versions. Endurance Characteristics Symbol Parameter Data Retention t DR Program/Erase Cycles N PE December 4, 1998 (Version 5.0) XC9536 In-System Programmable CPLD Parameter 1 Parameter 4.75 (4.5) Min 10,000 Value Units -0.5 to 7 0.5 ...

Page 4

... Min Min Max GND Max GND GND 1.0 MHz V = GND, No load 1.0 MHz XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Min Max Min Max Min Max Min Max Min Max 5.0 6.0 7.5 3.5 3.5 4.5 0.0 0.0 0.0 4.0 4.0 4.5 100.0 100.0 83.3 100.0 83.3 0.5 0.5 0.5 3.0 3.0 4.0 7.0 7.0 8.5 5.0 5.0 5.5 5 ...

Page 5

... PTA December 4, 1998 (Version 5.0) XC9536 In-System Programmable CPLD Output Type V V CCIO TEST 5.0 V 5.0 V 3 XC9536-5 XC9536-6 XC9536-7 XC9536-10 XC9536-15 Min Max Min Max Min Max Min Max Min Max 1.5 1.5 1.5 1.5 4.0 4.0 5.0 5.0 2.0 2.0 0.0 0.0 3.0 3 ...

Page 6

... Note: [1] Global control pin XC9536 Global, JTAG and Power Pins Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS CCINT V 3.3 V/5 V CCIO GND No Connects 6 BScan Function ...

Page 7

... Revise datasheet to reflect new AC characteristics and Internal Timing Parameters. 12/04/98 Revise datasheet to remove PCI compliancy statement and remove t December 4, 1998 (Version 5.0) XC9536 In-System Programmable CPLD XC9536 - Temperature Range Number of Pins Package Type Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier (PLCC) ...

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