PIC18F24K20-I/SS Microchip Technology, PIC18F24K20-I/SS Datasheet
PIC18F24K20-I/SS
Specifications of PIC18F24K20-I/SS
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PIC18F24K20-I/SS Summary of contents
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... Tool). 4. Perform a “Connect” operation to the device (Debugger>Connect). development tool used, the part number and Device Revision ID value appear in the Output window. Note: The DEVREV values for the various PIC18F24K20/ 25K20/44K20/45K20 silicon revisions are shown in Table 1. Revision ID for Silicon Revision (1) (11-bit ...
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... PIC18F24K20/25K20/44K20/45K20 TABLE 2: SILICON ISSUE SUMMARY Module Feature Number ECCP CCP1CON ECCP Full-Bridge mode MSSP SPI SPI Clock 2 MSSP I C™ Slew Rate ADC Offset 2 MSSP I C Receiving 2 MSSP I C Master mode MSSP SPI SPI Master MSSP SPI SPI Master MSSP SPI ...
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... PIC18F24K20/25K20/44K20/45K20 TABLE 2: SILICON ISSUE SUMMARY (CONTINUED) Module Feature Number EUSART Asynchronous Receive mode PORTB Interrupts Interrupt-on- Change ADC ADC Conversion ECCP Full-Bridge mode ECCP Full-Bridge mode MSSP SPI SPI Clock MSSP SPI SPI Master MSSP SPI SPI Master 2 2 MSSP I C™ ...
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... PIC18F24K20/25K20/44K20/45K20 Silicon Errata Issues Note 1: This document summarizes all silicon errata issues from all specified revisions of silicon. 2: Shaded cells in this section indicate latest silicon in production. 1. Module: ECCP Changing the CCP1M<3:0> bits of CCP1CON may cause the CCPR1H and CCPR1L registers to capture the value of Timer1. ...
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... PIC18F24K20/25K20/44K20/45K20 2 7. Module: MSSP Master mode is not functional (Rev. A4 only). Work around Use software to emulate Master mode. Affected Silicon Revisions Module: MSSP SPI In SPI Master mode, when the CKE bit is cleared and the SMP bit is set, the last bit of the incoming data stream (bit 0) at the SDI pin will not be sampled properly ...
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... PIC18F24K20/25K20/44K20/45K20 14. Module: Internal Fixed Voltage Reference (FVR) The FVRST bit of the CVRCON2 register activates prematurely (Rev. A4 and A7 only). Work around Wait an additional 20 µs after FVRST is sensed high before using the fixed voltage reference. Enable the FVR by setting the FVREN bit of the ...
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... PIC18F24K20/25K20/44K20/45K20 19. Module: POR The POR may release around 0.8V (below the POR rearm voltage of 1.2V, nominal) when V rises from below 0.60V (when BOR is not enabled) or 0.33V (when BOR is enabled). Work around Use Power-up Timer when operating with the EC, EXTRC or HFINTOSC oscillator modes. Ensure ...
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... PIC18F24K20/25K20/44K20/45K20 25. Module: Configuration Bits Bit 3 of CONFIG3H defaults to ‘0’ after a Bulk Erase instead of ‘1’ as specified in the data sheet. Work around Program the HFOFST bit to the desired state after ® a Bulk Erase. All MPLAB IDE programming tools currently perform this way. ...
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... PIC18F24K20/25K20/44K20/45K20 signal improperly starts immediately with the direc- tion change and stays on for T Prescale * DC1B[1:0]. Work around Avoid changing direction when the duty cycle is within three Least Significant steps of 100% duty cycle. Instead, clear the DC1B[1:0] bits before the direction change and then set them to the desired value after the direction change is complete ...
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... PIC18F24K20/25K20/44K20/45K20 2 34. Module: MSSP I C™ Master I C Receive mode if a Stop condition occurs in the middle of an address or data reception, then the SCL clock stream will continue endlessly and the RCEN bit of the SSPCON2 register will remain set improperly Start condition occurs after the improper Stop condition then 9 additional clocks will be generated followed by the RCEN bit going low ...
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... PIC18F24K20/25K20/44K20/45K20 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS41303G): None. 2010 Microchip Technology Inc. DS80425G-page 11 ...
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... PIC18F24K20/25K20/44K20/45K20 APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (12/2008) Initial release of this document. Rev B Document (05/2009) Updated Errata to new format; Added Module 11: PORTB and Module 12: ADC; minor edits. Clarifications/Corrections to the Data Sheet: Added Module 1: MSSP; Module 2: Electrical Specifications; Module 3: Electrical Specifications. Rev C Document (06/2009) ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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