PIC18F24K20-I/ML Microchip Technology, PIC18F24K20-I/ML Datasheet - Page 133
![IC PIC MCU FLASH 8KX16 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC18F24K20-I/ML
Manufacturer Part Number
PIC18F24K20-I/ML
Description
IC PIC MCU FLASH 8KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F24K20-I/ML
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
28QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Height
0.88 mm
Length
6 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V
Width
6 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F25K20T-ISS PDF datasheet #3
- PIC18F25K20T-ISS PDF datasheet #4
- PIC18F26K20-ISO PDF datasheet #5
- Current page: 133 of 430
- Download datasheet (7Mb)
10.6
Depending on the particular PIC18F2XK20/4XK20
device selected, PORTE is implemented in two
different ways.
10.6.1
For PIC18F4XK20 devices, PORTE is a 4-bit wide port.
Three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/
AN7) are individually configurable as inputs or outputs.
These pins have Schmitt Trigger input buffers. When
selected as an analog input, these pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., disable the output driver).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The upper four bits of the TRISE register also control
the operation of the Parallel Slave Port. Their operation
is explained in Register 10-1.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register, read and write the latched output value for
PORTE.
© 2008 Microchip Technology Inc.
Note:
PORTE, TRISE and LATE
Registers
PORTE IN PIC18F4XK20 DEVICES
On a Power-on Reset, RE<2:0> are
configured as analog inputs.
Preliminary
The fourth pin of PORTE (MCLR/V
only pin. Its operation is controlled by the MCLRE
Configuration bit. When selected as a port pin
(MCLRE = 0), it functions as a digital input only pin; as
such, it does not have TRIS or LAT bits associated with its
operation. Otherwise, it functions as the device’s Master
Clear input. In either configuration, RE3 also functions as
the programming voltage input during programming.
EXAMPLE 10-5:
10.6.2
For PIC18F2XK20 devices, PORTE is only available
when
(MCLR = 0). In these cases, PORTE is a single bit,
input only port comprised of RE3 only. The pin operates
as previously described.
PIC18F2XK20/4XK20
CLRF
CLRF
MOVLW
ANDWF
MOVLW
MOVWF
Note:
Master
PORTE
LATE
1Fh
ANSEL,w ; for digital only
05h
TRISE
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
PORTE IN PIC18F2XK20 DEVICES
Clear
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure analog pins
; Value used to
; initialize data
; direction
; Set RE<0> as input
; RE<1> as output
; RE<2> as input
INITIALIZING PORTE
functionality
PP
DS41303D-page 131
/RE3) is an input
is
disabled
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