ATMEGA48-20AU Atmel, ATMEGA48-20AU Datasheet - Page 227

IC AVR MCU 4K 20MHZ 5V 32TQFP

ATMEGA48-20AU

Manufacturer Part Number
ATMEGA48-20AU
Description
IC AVR MCU 4K 20MHZ 5V 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA48-20AU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA48x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire/SPI/USART/Serial
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
20MHz
Total Internal Ram Size
512Byte
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
32
Package Type
TQFP
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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21.7.3
2545S–AVR–07/10
Slave Receiver Mode
Figure 21-14. Formats and States in the Master Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter
(see
are zero or are masked to zero.
Figure 21-15. Data transfer in Slave Receiver mode
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR
value
Figure
Successfull
reception
from a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
SDA
SCL
21-15). All the status codes mentioned in this section assume that the prescaler bits
From master to slave
From slave to master
$08
S
TWA6
SLA
Device 1
RECEIVER
SLAVE
TWA5
R
MR
TRANSMITTER
Device 2
A or A
DATA
MASTER
$40
$48
$38
$68
A
A
A
$78
TWA4
Other master
Other master
n
continues
continues
Device’s Own Slave Address
P
$B0
Device 3
DATA
A
TWA3
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
........
$50
$38
To corresponding
states in slave mode
A
A
TWA2
Other master
Device n
DATA
continues
ATmega48/88/168
V
CC
$58
A
TWA1
R1
$10
P
R
S
R2
SLA
TWA0
W
R
TWGCE
MT
227

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