PIC18F14K22-I/ML Microchip Technology, PIC18F14K22-I/ML Datasheet - Page 99
![IC PIC MCU FLASH 512KX16 20-QFN](/photos/6/64/66481/c04-126_ml_sml.jpg)
PIC18F14K22-I/ML
Manufacturer Part Number
PIC18F14K22-I/ML
Description
IC PIC MCU FLASH 512KX16 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC18LF13K22-ISS.pdf
(388 pages)
3.PIC18LF13K22-ISS.pdf
(12 pages)
4.PIC18LF13K22-ISS.pdf
(36 pages)
5.PIC18F13K22-ISS.pdf
(382 pages)
Specifications of PIC18F14K22-I/ML
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-VQFN Exposed Pad, 20-HVQFN, 20-SQFN, 20-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
18
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
64MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, MSSP, SPI, USART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Package
20QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
A/d Bit Size
10 bit
A/d Channels Available
12
Height
0.88 mm
Length
4 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.8 V, 2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F14K22-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F722-ISS PDF datasheet
- PIC18LF13K22-ISS PDF datasheet #2
- PIC18LF13K22-ISS PDF datasheet #3
- PIC18LF13K22-ISS PDF datasheet #4
- PIC18F13K22-ISS PDF datasheet #5
- Current page: 99 of 382
- Download datasheet (6Mb)
FIGURE 9-2:
9.3
An 8-bit counter is available as a prescaler for the Timer0
module. The prescaler is not directly readable or writable;
its value is set by the PSA and T0PS<2:0> bits of the
T0CON
assignment and prescale ratio.
Clearing the PSA bit assigns the prescaler to the
Timer0 module. When the prescaler is assigned,
prescale values from 1:2 through 1:256 in integer
power-of-2 increments are selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF TMR0, MOVWF
TMR0, BSF TMR0, etc.) clear the prescaler count.
TABLE 9-1:
© 2009 Microchip Technology Inc.
INTCON
PORTA
TMR0H
TMR0L
TRISA
T0CON
Legend: Shaded cells are not used by Timer0.
Note:
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
T0CKI pin
Name
Prescaler
register
T0SE
T0CS
T0PS<2:0>
PSA
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count but will not change the prescaler
assignment.
Timer0 Register, High Byte
Timer0 Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
F
TMR0ON
OSC
Bit 7
RA7
REGISTERS ASSOCIATED WITH TIMER0
—
/4
which
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
0
1
determine
T08BIT
Bit 6
RA6
—
Programmable
Prescaler
TRISA5
3
the
T0CS
Bit 5
RA5
prescaler
0
1
Preliminary
TRISA4
INT0IE
T0SE
Bit 4
RA4
(2 T
Sync with
PIC18F1XK22/LF1XK22
Internal
Clocks
CY
Delay)
RABIE
9.3.1
The prescaler assignment is fully under software
control and can be changed “on-the-fly” during program
execution.
9.4
The TMR0 interrupt is generated when the TMR0 reg-
ister overflows from FFh to 00h in 8-bit mode, or from
FFFFh to 0000h in 16-bit mode. This overflow sets the
TMR0IF flag bit. The interrupt can be masked by clear-
ing the TMR0IE bit of the INTCON register. Before
re-enabling the interrupt, the TMR0IF bit must be
cleared by software in the Interrupt Service Routine.
Since Timer0 is shut down in Sleep mode, the TMR0
interrupt cannot awaken the processor from Sleep.
Bit 3
PSA
RA3
—
Timer0 Interrupt
TMR0IF
TRISA2
T0PS2
SWITCHING PRESCALER
ASSIGNMENT
Bit 2
RA2
TMR0L
8
8
TRISA1
INT0IF
T0PS1
Bit 1
RA1
High Byte
TMR0H
TMR0
8
8
8
TRISA0
T0PS0
RABIF
Bit 0
RA0
DS41365B-page 97
Set
TMR0IF
on Overflow
Read TMR0L
Write TMR0L
Internal Data Bus
on page
Values
Reset
249
252
250
250
252
250
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